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https://github.com/ryujinx-mirror/ryujinx.git
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36e8e074c9
* Fix and simplify TranslatorCache * Fix some assignment alignments, remove some unused usings * Changes to ILEmitter, separate it from ILEmitterCtx * Rename ILEmitter to ILMethodBuilder * Rename LdrLit and *_Fix opcodes * Revert TranslatorCache impl to the more performant one, fix a few issues with it * Allow EmitOpCode to be called even after everything has been emitted * Make Emit and AdvanceOpCode private, simplify it a bit now that it starts emiting from the entry point * Remove unneeded temp use * Add missing exit call on TestExclusive * Use better hash * Implement the == and != operators
46 lines
1.4 KiB
C#
46 lines
1.4 KiB
C#
using ChocolArm64.State;
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using System.Reflection.Emit;
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namespace ChocolArm64.Translation
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{
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struct ILOpCodeLoad : IILEmit
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{
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public int Index { get; private set; }
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public IoType IoType { get; private set; }
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public RegisterSize RegisterSize { get; private set; }
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public ILOpCodeLoad(int index, IoType ioType, RegisterSize registerSize = 0)
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{
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Index = index;
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IoType = ioType;
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RegisterSize = registerSize;
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}
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public void Emit(ILMethodBuilder context)
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{
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switch (IoType)
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{
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case IoType.Arg: context.Generator.EmitLdarg(Index); break;
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case IoType.Flag: EmitLdloc(context, Index, RegisterType.Flag); break;
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case IoType.Int: EmitLdloc(context, Index, RegisterType.Int); break;
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case IoType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break;
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}
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}
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private void EmitLdloc(ILMethodBuilder context, int index, RegisterType registerType)
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{
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Register reg = new Register(index, registerType);
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context.Generator.EmitLdloc(context.GetLocalIndex(reg));
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if (registerType == RegisterType.Int &&
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RegisterSize == RegisterSize.Int32)
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{
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context.Generator.Emit(OpCodes.Conv_U4);
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}
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}
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}
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} |