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https://github.com/ryujinx-mirror/ryujinx.git
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e21ebbf666
* Add optimizations related to caller/callee saved registers, thread synchronization and disable tier 0 * Refactoring * Add a config entry to enable or disable the reg load/store opt. * Remove unnecessary register state stores for calls when the callee is know * Rename IoType to VarType * Enable tier 0 while fixing some perf issues related to tier 0 * Small tweak -- Compile before adding to the cache, to avoid lags * Add required config entry
81 lines
2.0 KiB
C#
81 lines
2.0 KiB
C#
using ChocolArm64.Decoders;
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using ChocolArm64.State;
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using ChocolArm64.Translation;
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using System.Reflection.Emit;
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using static ChocolArm64.Instructions.InstEmit32Helper;
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namespace ChocolArm64.Instructions
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{
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static partial class InstEmit32
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{
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public static void B(ILEmitterCtx context)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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if (context.CurrBlock.Branch != null)
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{
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context.Emit(OpCodes.Br, context.GetLabel(op.Imm));
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}
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else
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{
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context.EmitStoreState();
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context.EmitLdc_I8(op.Imm);
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context.Emit(OpCodes.Ret);
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}
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}
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public static void Bl(ILEmitterCtx context)
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{
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Blx(context, x: false);
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}
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public static void Blx(ILEmitterCtx context)
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{
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Blx(context, x: true);
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}
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public static void Bx(ILEmitterCtx context)
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{
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IOpCode32BReg op = (IOpCode32BReg)context.CurrOp;
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context.EmitStoreState();
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EmitLoadFromRegister(context, op.Rm);
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EmitBxWritePc(context);
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}
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private static void Blx(ILEmitterCtx context, bool x)
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{
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IOpCode32BImm op = (IOpCode32BImm)context.CurrOp;
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uint pc = op.GetPc();
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bool isThumb = IsThumb(context.CurrOp);
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if (!isThumb)
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{
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context.EmitLdc_I(op.GetPc() - 4);
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}
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else
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{
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context.EmitLdc_I(op.GetPc() | 1);
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}
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context.EmitStint(GetBankedRegisterAlias(context.Mode, RegisterAlias.Aarch32Lr));
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//If x is true, then this is a branch with link and exchange.
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//In this case we need to swap the mode between Arm <-> Thumb.
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if (x)
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{
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context.EmitLdc_I4(isThumb ? 0 : 1);
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context.EmitStflg((int)PState.TBit);
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}
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InstEmitFlowHelper.EmitCall(context, op.Imm);
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}
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}
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} |