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c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table |
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| .. | ||
| Exceptions | ||
| FileSystem | ||
| HOS | ||
| Input | ||
| Loaders | ||
| Resource | ||
| Utilities | ||
| DeviceMemory.cs | ||
| Homebrew.npdm | ||
| PerformanceStatistics.cs | ||
| Ryujinx.HLE.csproj | ||
| RyujinxProfileImage.jpg | ||
| Switch.cs | ||
