1
0
mirror of https://github.com/tdaede/td-io.git synced 2024-11-27 16:10:50 +01:00

Update PCB to v1.4

This commit is contained in:
Thomas Daede 2023-03-01 20:40:12 -08:00
parent b37abeb8ce
commit 12b1a718ed
4 changed files with 19558 additions and 19486 deletions

File diff suppressed because it is too large Load Diff

View File

@ -1,5 +1,6 @@
{
"board": {
"3dviewports": [],
"design_settings": {
"defaults": {
"board_outline_line_width": 0.049999999999999996,
@ -72,20 +73,26 @@
"rule_severities": {
"annular_width": "error",
"clearance": "error",
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
"duplicate_footprints": "warning",
"extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error",
"hole_clearance": "error",
"hole_near_hole": "error",
"invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error",
"items_not_allowed": "error",
"length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error",
"microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore",
@ -95,9 +102,14 @@
"padstack": "error",
"pth_inside_courtyard": "ignore",
"shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning",
"silk_overlap": "warning",
"skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
"text_thickness": "warning",
"through_hole_pad_without_hole": "error",
"too_many_vias": "error",
"track_dangling": "warning",
@ -106,7 +118,6 @@
"unconnected_items": "error",
"unresolved_variable": "error",
"via_dangling": "warning",
"zone_has_empty_net": "error",
"zones_intersect": "error"
},
"rule_severitieslegacy_courtyards_overlap": true,
@ -116,18 +127,63 @@
"allow_microvias": false,
"max_error": 0.005,
"min_clearance": 0.16,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.024999999999999998,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 2,
"min_silk_clearance": 0.0,
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.08,
"min_through_hole_diameter": 0.19999999999999998,
"min_track_width": 0.19999999999999998,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_to_copper_clearance": 0.0,
"use_height_for_length_calcs": true
},
"teardrop_options": [
{
"td_allow_use_two_tracks": true,
"td_curve_segcount": 5,
"td_on_pad_in_zone": false,
"td_onpadsmd": true,
"td_onroundshapesonly": false,
"td_ontrackend": false,
"td_onviapad": true
}
],
"teardrop_parameters": [
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_round_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_rect_shape",
"td_width_to_size_filter_ratio": 0.9
},
{
"td_curve_segcount": 0,
"td_height_ratio": 1.0,
"td_length_ratio": 0.5,
"td_maxheight": 2.0,
"td_maxlen": 1.0,
"td_target_name": "td_track_end",
"td_width_to_size_filter_ratio": 0.9
}
],
"track_widths": [
0.0,
0.4,
@ -333,18 +389,23 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
@ -354,6 +415,7 @@
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
@ -371,7 +433,7 @@
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"bus_width": 12,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
@ -385,13 +447,15 @@
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
"wire_width": 6
}
],
"meta": {
"version": 2
"version": 3
},
"net_colors": null
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
},
"pcbnew": {
"last_paths": {
@ -407,6 +471,8 @@
"schematic": {
"annotate_start_num": 0,
"drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
@ -438,7 +504,11 @@
"page_layout_descr_file": "",
"plot_directory": "v1.1/",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,
"subpart_id_separator": 0
},

File diff suppressed because it is too large Load Diff

View File

@ -0,0 +1,72 @@
(footprint "Vishay_PowerPAK_MLP44-24L" (version 20211014) (generator pcbnew)
(layer "F.Cu")
(tedit 0)
(attr smd)
(fp_text reference "REF**" (at 0 -3.4 unlocked) (layer "F.SilkS")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp c4f57582-4080-45a6-a9b5-4be5dc62757b)
)
(fp_text value "Vishay_PowerPAK_MLP44-24L" (at 0.045 3.625 unlocked) (layer "F.Fab")
(effects (font (size 1 1) (thickness 0.15)))
(tstamp f0072e3b-764d-4f62-befa-15d6bbdb13ce)
)
(fp_line (start 1.775 -2.125) (end 2.12 -2.125) (layer "F.SilkS") (width 0.12) (tstamp 0258c08a-be92-4edf-93b5-134521353f54))
(fp_line (start 2.12 2.125) (end 2.12 1.65) (layer "F.SilkS") (width 0.12) (tstamp 08b975fd-792f-4845-bd45-aa94a9715019))
(fp_line (start -2.1375 2.125) (end -2.1375 1.65) (layer "F.SilkS") (width 0.12) (tstamp 13853726-09ca-40f2-87c3-a8956bc4af4f))
(fp_line (start -1.8 2.125) (end -2.1375 2.125) (layer "F.SilkS") (width 0.12) (tstamp 30a2eafc-94ad-42f6-a273-320ae0170f00))
(fp_line (start 2.12 -2.125) (end 2.12 -1.65) (layer "F.SilkS") (width 0.12) (tstamp 959548e4-215a-42fe-85b9-49abc835c8f6))
(fp_line (start -1.775 -2.125) (end -2.1625 -2.125) (layer "F.SilkS") (width 0.12) (tstamp b65a6a12-0d08-40f3-8ed6-a5edbc348e2e))
(fp_line (start 1.645 2.125) (end 2.12 2.125) (layer "F.SilkS") (width 0.12) (tstamp d1c96f7d-e91d-431f-ac4e-25d37441b0c2))
(fp_rect (start -2 -2) (end 2 2) (layer "Dwgs.User") (width 0.01) (fill none) (tstamp 67dd1d71-2fd5-454b-b66d-8bf245fffe1f))
(fp_rect (start -2.5 -2.5) (end 2.5 2.5) (layer "F.CrtYd") (width 0.12) (fill none) (tstamp 6f608cd3-f53a-40f2-a369-38a6dae4322e))
(pad "1" smd rect (at -1.9375 -0.825 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 6bdd9c3c-efac-4a57-bb07-e6683205632f))
(pad "2" smd rect (at -1.9375 -0.375 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp eb99ee24-a3c5-4771-885a-b57f683a81bf))
(pad "3" smd rect (at -1.9375 0.525 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp fd724dea-5ddf-4dc5-b197-1222f863928b))
(pad "4" smd rect (at -1.9375 0.975 270) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 47b7fa05-79cf-4553-b55a-b508ddfa70b6))
(pad "5" smd rect (at -1.475 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 63ca9e0d-a75e-46da-904b-483a5ea040d0))
(pad "5" smd rect (at -0.45 1.7125) (size 2.35 0.275) (layers "F.Cu" "F.Mask")
(solder_paste_margin -0.25) (tstamp 97c285fd-8323-4270-8825-22d29170abf0))
(pad "6" smd rect (at -1.025 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp eb0f64ec-086d-404a-8d10-8cdc064dd95c))
(pad "7" smd rect (at -0.575 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp f0c1cf97-5213-4ff7-91e7-c14dd4cb4024))
(pad "8" smd rect (at 0.125 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a730d9f1-4d83-4dcc-ba50-2565132a7c7c))
(pad "9" smd rect (at 0.575 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 17f6e4b1-f741-42f9-8ed9-6f1502385d96))
(pad "10" smd rect (at 1.025 1.9375 180) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7eeef101-2e2f-4d42-8199-398d3debdf3a))
(pad "11" smd rect (at 1.9375 1.425 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 93dfc21f-0329-45de-8023-66c36e70f4ab))
(pad "12" smd rect (at 1.9375 0.975 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 74a9825e-2496-4ee4-be7e-f330ba87976b))
(pad "13" smd rect (at 1.9375 0.525 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 136e9043-9d9b-4add-a5a0-c96121d24080))
(pad "14" smd rect (at 1.9375 0.075 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 39cbdfe8-4219-489a-b4b0-f7bedc4a85bf))
(pad "15" smd rect (at 1.9375 -0.375 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 57012bd4-7a89-4c9a-9d58-64dfe4df17cc))
(pad "16" smd rect (at 1.9375 -0.825 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp a91e522a-17a8-4f9b-a0e3-f4ee5d8c32d9))
(pad "17" smd rect (at 1.9375 -1.275 90) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 7d8cd1b5-f705-49aa-9f3f-48448af87fb2))
(pad "18" smd rect (at 1.475 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 866dc468-d99d-41c0-9910-848a99f6fbd7))
(pad "19" smd rect (at 1.025 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4c1ba172-4f35-4009-8d7e-0828fa740a34))
(pad "20" smd rect (at 0.575 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 2895ff56-09b0-46dd-86ee-edf0fd324071))
(pad "21" smd rect (at 0.125 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp e98ce279-a0ab-4dbd-b5f4-222b121fdd94))
(pad "22" smd rect (at -0.575 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp d3ef78ce-773c-4241-8dda-5d93241ca604))
(pad "23" smd rect (at -1.025 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 976a6cb8-eccc-4a3f-897b-8a4695cb224f))
(pad "24" smd rect (at -1.475 -1.9375) (size 0.3 0.725) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 92780cda-ec1c-4999-83e3-268cade2a316))
(pad "25" smd rect (at 0.4875 -0.75) (size 1.575 1.05) (layers "F.Cu" "F.Paste" "F.Mask")
(solder_paste_margin -0.25) (tstamp 7b6e123f-2ca8-4dd5-a8b2-190dad2a441d))
(pad "26" smd rect (at -1.175 -0.75) (size 1.15 1.05) (layers "F.Cu" "F.Paste" "F.Mask")
(solder_paste_margin -0.25) (tstamp f95ccdc9-0b3f-4e01-951a-2e822c448cd0))
(pad "27" smd custom (at -0.6625 0.675) (size 2.175 1.2) (layers "F.Cu" "F.Paste" "F.Mask")
(solder_paste_margin -0.25)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy 1.7375 -0.145)
(xy 1.0875 -0.145)
(xy 1.0875 0.6)
(xy -1.0875 0.6)
(xy -1.0875 -0.6)
(xy 1.7375 -0.6)
) (width 0) (fill yes))
(gr_rect (start 1.0875 -0.6) (end 1.7375 -0.145) (width 0) (fill yes))
) (tstamp 3445a491-b638-454d-9c2c-20ae481cc70f))
(pad "28" smd rect (at 0.985 0.99) (size 0.58 0.38) (layers "F.Cu" "F.Paste" "F.Mask") (tstamp 4e9c65ee-82f1-4318-a1c8-de0c1cf776cc))
(model "${KICAD6_3DMODEL_DIR}/Package_DFN_QFN.3dshapes/WQFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm.step"
(offset (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)