mirror of
https://github.com/tdaede/td-io.git
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Add JVS chaining support
This commit is contained in:
Thomas Daede
parent
0a6f31d8dc
commit
196180bd3b
256
td-io-cache.lib
256
td-io-cache.lib
@ -123,6 +123,32 @@ X VDD 6 -100 300 150 D 50 40 3 1 W
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ENDDRAW
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ENDDEF
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#
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# Amplifier_Operational_TL081
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#
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DEF Amplifier_Operational_TL081 U 0 5 Y Y 1 F N
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F0 "U" 0 250 50 H V L CNN
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F1 "Amplifier_Operational_TL081" 0 150 50 H V L CNN
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F2 "" 50 50 50 H I C CNN
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F3 "" 150 150 50 H I C CNN
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ALIAS AD8610 LF155 LF156 LF256 LF257 LF355 LF356 LF357 TL081 TL061 TL071
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$FPLIST
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SOIC*3.9x4.9mm*P1.27mm*
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DIP*W7.62mm*
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TSSOP*3x3mm*P0.65mm*
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$ENDFPLIST
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DRAW
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P 4 0 1 10 -200 200 200 0 -200 -200 -200 200 f
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X NULL 1 0 -300 200 U 50 20 1 1 I
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X - 2 -300 -100 100 R 50 50 1 1 I
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X + 3 -300 100 100 R 50 50 1 1 I
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X V- 4 -100 -300 150 U 50 50 1 1 W
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X NULL 5 100 -300 250 U 50 20 1 1 I
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X ~ 6 300 0 100 L 50 50 1 1 O
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X V+ 7 -100 300 150 D 50 50 1 1 W
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X NC 8 0 100 100 D 50 50 1 1 N N
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ENDDRAW
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ENDDEF
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#
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# Amplifier_Video_AD813
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#
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DEF Amplifier_Video_AD813 U 0 5 Y Y 4 L N
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@ -428,48 +454,6 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_CP
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#
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DEF Device_CP C 0 10 N Y 1 F N
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F0 "C" 25 100 50 H V L CNN
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F1 "Device_CP" 25 -100 50 H V L CNN
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F2 "" 38 -150 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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CP_*
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$ENDFPLIST
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DRAW
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S -90 20 90 40 0 1 0 N
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S 90 -20 -90 -40 0 1 0 F
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P 2 0 1 0 -70 90 -30 90 N
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P 2 0 1 0 -50 110 -50 70 N
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X ~ 1 0 150 110 D 50 50 1 1 P
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X ~ 2 0 -150 110 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_D_Schottky
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#
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DEF Device_D_Schottky D 0 40 N N 1 F N
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F0 "D" 0 100 50 H V C CNN
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F1 "Device_D_Schottky" 0 -100 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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TO-???*
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*_Diode_*
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*SingleDiode*
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D_*
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$ENDFPLIST
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DRAW
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P 2 0 1 0 50 0 -50 0 N
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P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
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P 6 0 1 10 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
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X K 1 -150 0 100 R 50 50 1 1 P
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X A 2 150 0 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Device_L
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#
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DEF Device_L L 0 40 N N 1 F N
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@ -563,40 +547,56 @@ X ~ 3 0 -200 200 U 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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# Interface_UART_ST485EBDR
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# Diode_BAV99S
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#
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DEF Interface_UART_ST485EBDR U 0 20 Y Y 1 F N
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F0 "U" -250 350 50 H V C CNN
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F1 "Interface_UART_ST485EBDR" 50 350 50 H V L CNN
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F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -900 50 H I C CNN
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F3 "" 0 50 50 H I C CNN
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DEF Diode_BAV99S D 0 1 Y N 2 L N
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F0 "D" 0 100 50 H V C CNN
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F1 "Diode_BAV99S" 0 200 50 H V C CNN
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F2 "Package_TO_SOT_SMD:SOT-363_SC-70-6" 0 -500 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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ALIAS BAV199DW
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$FPLIST
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SOT?363*
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$ENDFPLIST
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DRAW
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C 0 0 10 0 1 0 F
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P 2 0 1 0 -200 0 200 0 N
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P 2 0 1 0 0 0 0 -100 N
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P 3 0 1 10 -50 -50 -50 50 -50 50 N
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P 3 0 1 10 150 50 150 -50 150 -50 N
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P 6 0 1 10 -150 50 -50 0 -150 -50 -150 50 -150 50 -150 50 N
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P 6 0 1 10 50 50 150 0 50 -50 50 50 50 50 50 50 N
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P 2 1 1 0 250 0 300 0 N
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P 2 2 1 0 250 0 300 0 N
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X A1 1 -300 0 100 R 50 50 1 1 P
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X K2 2 300 0 100 L 50 50 1 1 P
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X K3A4 6 0 -200 100 U 50 50 1 1 P
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X K1A2 3 0 -200 100 U 50 50 2 1 P
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X A3 4 -300 0 100 R 50 50 2 1 P
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X K4 5 300 0 100 L 50 50 2 1 P
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ENDDRAW
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ENDDEF
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#
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# Interface_UART_SP3481CN
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#
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DEF Interface_UART_SP3481CN U 0 40 Y Y 1 F N
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F0 "U" -300 350 50 H V L CNN
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F1 "Interface_UART_SP3481CN" 100 350 50 H V L CNN
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F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 1050 -350 50 H I C CIN
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F3 "" 0 0 50 H I C CNN
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ALIAS MAX3072E MAX3075E MAX3078E SP3481EN SP3485CN SP3485EN
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$FPLIST
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SOIC*3.9x4.9mm*P1.27mm*
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$ENDFPLIST
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DRAW
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C -12 -145 14 0 1 10 F
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C -1 59 14 0 1 10 F
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C 65 75 14 0 1 10 F
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S -300 300 300 -400 0 1 10 f
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S 50 125 50 125 0 1 0 N
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P 2 0 1 10 -160 -200 -75 -200 N
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P 2 0 1 10 -160 100 -50 100 N
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P 2 0 1 10 -50 -126 -50 -136 N
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P 2 0 1 10 -25 -200 210 -200 N
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P 3 0 1 10 -160 -100 -50 -100 -50 -125 N
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P 3 0 1 10 0 50 0 0 -160 0 N
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P 3 0 1 10 50 125 150 125 150 -200 N
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P 3 0 1 10 100 75 100 -150 0 -150 N
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P 4 0 1 10 -75 -125 -75 -225 25 -175 -75 -125 N
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P 4 0 1 10 -50 100 50 150 50 50 -50 100 N
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P 4 0 1 10 75 75 175 75 175 100 210 100 N
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X RO 1 -400 100 100 R 50 50 1 1 O
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X ~RE 2 -400 0 100 R 50 50 1 1 I
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S -300 300 300 -300 0 1 10 f
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X RO 1 -400 200 100 R 50 50 1 1 O
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X ~RE~ 2 -400 100 100 R 50 50 1 1 I
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X DE 3 -400 -100 100 R 50 50 1 1 I
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X DI 4 -400 -200 100 R 50 50 1 1 I
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X GND 5 0 -500 100 U 50 50 1 1 W
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X A 6 400 -200 100 L 50 50 1 1 B
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X B 7 400 100 100 L 50 50 1 1 B
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X GND 5 0 -400 100 U 50 50 1 1 W
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X A 6 400 100 100 L 50 50 1 1 B
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X B 7 400 -100 100 L 50 50 1 1 B
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X VCC 8 0 400 100 D 50 50 1 1 W
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ENDDRAW
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ENDDEF
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@ -657,6 +657,22 @@ X GPIO6 9 -700 150 100 R 50 50 1 1 B
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ENDDRAW
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ENDDEF
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#
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# Mechanical_MountingHole_Pad
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#
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DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
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F0 "H" 0 250 50 H V C CNN
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F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
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F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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$FPLIST
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MountingHole*Pad*
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$ENDFPLIST
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DRAW
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C 0 50 50 0 1 50 N
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X 1 1 0 -100 100 U 50 50 1 1 I
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ENDDRAW
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ENDDEF
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#
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# Memory_EEPROM_AT24CS01-SSHM
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#
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DEF Memory_EEPROM_AT24CS01-SSHM U 0 20 Y Y 1 F N
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@ -681,26 +697,55 @@ X VCC 8 0 300 100 D 50 50 1 1 W
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ENDDRAW
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ENDDEF
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#
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# Regulator_Switching_LM25085MM
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# Relay_SolidState_CPC1017N
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#
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DEF Regulator_Switching_LM25085MM U 0 20 Y Y 1 F N
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F0 "U" -300 450 50 H V L CNN
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F1 "Regulator_Switching_LM25085MM" -50 450 50 H V L CNN
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F2 "Package_SO:MSOP-8_3x3mm_P0.65mm" 50 -450 50 H I L CIN
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F3 "" 0 0 50 H I C CNN
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DEF Relay_SolidState_CPC1017N U 0 20 Y Y 1 F N
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F0 "U" -200 200 50 H V L CNN
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F1 "Relay_SolidState_CPC1017N" 0 200 50 H V L CNN
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F2 "Package_SO:SOP-4_3.8x4.1mm_P2.54mm" -200 -200 50 H I L CIN
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F3 "" -50 0 50 H I L CNN
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ALIAS CPC1117N
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$FPLIST
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MSOP*3x3mm*P0.65mm*
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SOP*3.8x4.1mm*P2.54mm*
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$ENDFPLIST
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DRAW
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S -300 400 300 -400 0 1 10 f
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X ADJ 1 400 100 100 L 50 50 1 1 I
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X RT 2 -400 -200 100 R 50 50 1 1 I
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X FB 3 400 -300 100 L 50 50 1 1 I
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X GND 4 0 -500 100 U 50 50 1 1 W
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X ISEN 5 400 -100 100 L 50 50 1 1 I
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X PGATE 6 400 0 100 L 50 50 1 1 O
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X VCC 7 400 300 100 L 50 50 1 1 w
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X VIN 8 -400 300 100 R 50 50 1 1 W
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C 110 -25 5 0 1 0 N
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C 110 0 5 0 1 0 N
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C 110 25 5 0 1 0 N
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C 150 -100 5 0 1 0 N
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C 150 0 5 0 1 0 N
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C 150 100 5 0 1 0 N
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S -200 150 200 -150 0 1 10 f
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P 2 0 1 0 -150 -25 -100 -25 N
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P 2 0 1 8 40 -25 40 -85 N
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P 2 0 1 8 40 85 40 25 N
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P 2 0 1 14 60 -20 60 -30 N
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P 2 0 1 0 110 0 150 0 N
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P 2 0 1 0 135 -65 165 -65 N
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P 2 0 1 0 135 65 165 65 N
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P 2 0 1 0 150 -100 150 100 N
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P 3 0 1 14 60 -80 60 -90 60 -90 N
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P 3 0 1 14 60 -50 60 -60 60 -60 N
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P 3 0 1 14 60 30 60 20 60 20 N
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P 3 0 1 14 60 60 60 50 60 50 N
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P 3 0 1 14 60 90 60 80 60 80 N
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P 3 0 1 0 65 -55 110 -55 110 -25 N
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P 3 0 1 0 65 55 110 55 110 25 N
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P 4 0 1 0 -200 100 -125 100 -125 -100 -200 -100 N
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P 4 0 1 0 -125 -25 -150 25 -100 25 -125 -25 N
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P 4 0 1 0 65 -85 110 -85 110 -100 200 -100 N
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P 4 0 1 0 65 -25 110 -25 110 25 65 25 N
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P 4 0 1 0 65 85 110 85 110 100 200 100 N
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P 4 0 1 0 70 -55 90 -50 90 -60 70 -55 N
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P 4 0 1 0 70 55 90 60 90 50 70 55 N
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P 4 0 1 0 150 -65 135 -35 165 -35 150 -65 N
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P 4 0 1 0 150 65 135 35 165 35 150 65 N
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P 5 0 1 0 -75 -20 -25 -20 -40 -25 -40 -15 -25 -20 N
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P 5 0 1 0 -75 20 -25 20 -40 15 -40 25 -25 20 N
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X ~ 1 -300 100 100 R 50 50 1 1 P
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X ~ 2 -300 -100 100 R 50 50 1 1 P
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X ~ 3 300 -100 100 L 50 50 1 1 P
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X ~ 4 300 100 100 L 50 50 1 1 P
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ENDDRAW
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ENDDEF
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#
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@ -736,7 +781,6 @@ F0 "Q" 200 75 50 H V L CNN
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F1 "Transistor_FET_FDS6930A" 200 0 50 H V L CNN
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F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -75 50 H I L CIN
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F3 "" 0 0 50 H I L CNN
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ALIAS FDS6892A FDS6898A FDS9926A STS2DNE60 FDS6930A FDS6930B
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$FPLIST
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SOIC*3.9x4.9mm*P1.27mm*
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$ENDFPLIST
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@ -766,15 +810,16 @@ X D2 6 100 200 100 D 50 50 2 1 P N
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ENDDRAW
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ENDDEF
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#
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# Transistor_FET_Si7141DP
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# Transistor_FET_FDS6930B
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#
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DEF Transistor_FET_Si7141DP Q 0 20 Y N 1 F N
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DEF Transistor_FET_FDS6930B Q 0 20 Y N 2 F N
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F0 "Q" 200 75 50 H V L CNN
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F1 "Transistor_FET_Si7141DP" 200 0 50 H V L CNN
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F2 "Package_SO:PowerPAK_SO-8_Single" 200 -75 50 H I L CIN
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F1 "Transistor_FET_FDS6930B" 200 0 50 H V L CNN
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F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -75 50 H I L CIN
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F3 "" 0 0 50 H I L CNN
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ALIAS FDS6892A FDS6898A FDS9926A STS2DNE60 FDS6930A FDS6930B
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$FPLIST
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PowerPAK*SO*Single*
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SOIC*3.9x4.9mm*P1.27mm*
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$ENDFPLIST
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DRAW
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C 65 0 110 0 1 10 N
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@ -787,15 +832,18 @@ P 2 0 1 10 30 20 30 -20 N
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P 2 0 1 10 30 90 30 50 N
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P 2 0 1 0 100 100 100 70 N
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P 3 0 1 0 100 -100 100 0 30 0 N
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P 4 0 1 0 30 70 130 70 130 -70 30 -70 N
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P 4 0 1 0 90 0 50 15 50 -15 90 0 F
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P 4 0 1 0 110 -20 115 -15 145 -15 150 -10 N
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P 4 0 1 0 130 -15 115 10 145 10 130 -15 N
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X S 1 100 -200 100 U 50 50 1 1 P
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X S 2 100 -200 100 U 50 50 1 1 P N
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X S 3 100 -200 100 U 50 50 1 1 P N
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X G 4 -200 0 100 R 50 50 1 1 I
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X D 5 100 200 100 D 50 50 1 1 P
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P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
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P 4 0 1 0 40 0 80 15 80 -15 40 0 F
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P 4 0 1 0 110 20 115 15 145 15 150 10 N
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P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
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X S1 1 100 -200 100 U 50 50 1 1 P
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X G1 2 -200 0 100 R 50 50 1 1 P
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X D1 7 100 200 100 D 50 50 1 1 P N
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X D1 8 100 200 100 D 50 50 1 1 P
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X S2 3 100 -200 100 U 50 50 2 1 P
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X G2 4 -200 0 100 R 50 50 2 1 P
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X D2 5 100 200 100 D 50 50 2 1 P
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X D2 6 100 200 100 D 50 50 2 1 P N
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ENDDRAW
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ENDDEF
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#
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@ -943,7 +991,7 @@ X -5V E 1550 -500 100 L 50 50 1 1 w
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X +12V F 1550 -600 100 L 50 50 1 1 w
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X Meter_1 J 1550 -800 100 L 50 50 1 1 C
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X Lockout_1 K 1550 -900 100 L 50 50 1 1 C
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X Speaker- K 1550 -1000 100 L 50 50 1 1 I
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X Speaker- L 1550 -1000 100 L 50 50 1 1 I
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X Unused M 1550 -1100 100 L 50 50 1 1 N
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X Video_Green N 1550 -1200 100 L 50 50 1 1 I
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X Video_Sync P 1550 -1300 100 L 50 50 1 1 I
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@ -974,7 +1022,6 @@ F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S 0 -50 1050 -900 0 1 0 f
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X GND 0 800 -1000 100 U 50 50 1 1 W
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X VBST 1 1150 -450 100 L 50 50 1 1 I
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X SS 11 1150 -850 100 L 50 50 1 1 I
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X EN 12 -100 -550 100 R 50 50 1 1 I
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@ -983,13 +1030,14 @@ X FB 14 1150 -600 100 L 50 50 1 1 I
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X MODE 15 -100 -650 100 R 50 50 1 1 I
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X VCC 17 -100 -850 100 R 50 50 1 1 O
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X GND 18 700 -1000 100 U 50 50 1 1 W
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X SW 19 1150 -250 100 L 50 50 1 1 O
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X SW 19 1150 -250 100 L 50 50 1 1 P
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X VIN 2 -100 -150 100 R 50 50 1 1 W
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X SW 20 1150 -150 100 L 50 50 1 1 O
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X GND 21 800 -1000 100 U 50 50 1 1 W
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X VIN 3 -100 -250 100 R 50 50 1 1 W
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X VIN 4 -100 -350 100 R 50 50 1 1 W
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X VIN 5 -100 -450 100 R 50 50 1 1 W
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X SW 6 1150 -350 100 L 50 50 1 1 O
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X SW 6 1150 -350 100 L 50 50 1 1 P
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X GND 7 500 -1000 100 U 50 50 1 1 W
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X GND 8 600 -1000 100 U 50 50 1 1 W
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X PGOOD 9 -100 -750 100 R 50 50 1 1 C
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9228
td-io.kicad_pcb
9228
td-io.kicad_pcb
File diff suppressed because it is too large
Load Diff
@ -45,7 +45,7 @@ X -5V E 1550 -500 100 L 50 50 1 1 w
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X +12V F 1550 -600 100 L 50 50 1 1 w
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X Meter_1 J 1550 -800 100 L 50 50 1 1 C
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X Lockout_1 K 1550 -900 100 L 50 50 1 1 C
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X Speaker- K 1550 -1000 100 L 50 50 1 1 I
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X Speaker- L 1550 -1000 100 L 50 50 1 1 I
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X Unused M 1550 -1100 100 L 50 50 1 1 N
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X Video_Green N 1550 -1200 100 L 50 50 1 1 I
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X Video_Sync P 1550 -1300 100 L 50 50 1 1 I
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@ -76,7 +76,6 @@ F2 "" 0 0 50 H I C CNN
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F3 "" 0 0 50 H I C CNN
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DRAW
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S 0 -50 1050 -900 0 1 0 f
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X GND 0 800 -1000 100 U 50 50 1 1 W
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X VBST 1 1150 -450 100 L 50 50 1 1 I
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X SS 11 1150 -850 100 L 50 50 1 1 I
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X EN 12 -100 -550 100 R 50 50 1 1 I
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@ -85,13 +84,14 @@ X FB 14 1150 -600 100 L 50 50 1 1 I
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X MODE 15 -100 -650 100 R 50 50 1 1 I
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X VCC 17 -100 -850 100 R 50 50 1 1 O
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X GND 18 700 -1000 100 U 50 50 1 1 W
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X SW 19 1150 -250 100 L 50 50 1 1 O
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X SW 19 1150 -250 100 L 50 50 1 1 P
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X VIN 2 -100 -150 100 R 50 50 1 1 W
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X SW 20 1150 -150 100 L 50 50 1 1 O
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X GND 21 800 -1000 100 U 50 50 1 1 W
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X VIN 3 -100 -250 100 R 50 50 1 1 W
|
||||
X VIN 4 -100 -350 100 R 50 50 1 1 W
|
||||
X VIN 5 -100 -450 100 R 50 50 1 1 W
|
||||
X SW 6 1150 -350 100 L 50 50 1 1 O
|
||||
X SW 6 1150 -350 100 L 50 50 1 1 P
|
||||
X GND 7 500 -1000 100 U 50 50 1 1 W
|
||||
X GND 8 600 -1000 100 U 50 50 1 1 W
|
||||
X PGOOD 9 -100 -750 100 R 50 50 1 1 C
|
||||
|
||||
249
td-io.pro
249
td-io.pro
@ -1,29 +1,10 @@
|
||||
update=22/05/2015 07:44:53
|
||||
update=Fri 05 Feb 2021 09:21:46 PM PST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[pcbnew]
|
||||
version=1
|
||||
LastNetListRead=
|
||||
UseCmpFile=1
|
||||
PadDrill=0.600000000000
|
||||
PadDrillOvalY=0.600000000000
|
||||
PadSizeH=1.500000000000
|
||||
PadSizeV=1.500000000000
|
||||
PcbTextSizeV=1.500000000000
|
||||
PcbTextSizeH=1.500000000000
|
||||
PcbTextThickness=0.300000000000
|
||||
ModuleTextSizeV=1.000000000000
|
||||
ModuleTextSizeH=1.000000000000
|
||||
ModuleTextSizeThickness=0.150000000000
|
||||
SolderMaskClearance=0.000000000000
|
||||
SolderMaskMinWidth=0.000000000000
|
||||
DrawSegmentWidth=0.200000000000
|
||||
BoardOutlineThickness=0.100000000000
|
||||
ModuleOutlineThickness=0.150000000000
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
@ -31,3 +12,231 @@ NetIExt=net
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=1
|
||||
TrackWidth3=2.5
|
||||
ViaDiameter1=0.8
|
||||
ViaDrill1=0.4
|
||||
ViaDiameter2=1.2
|
||||
ViaDrill2=0.6
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.8
|
||||
ViaDrill=0.4
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user