early-access version 3276
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@ -1,7 +1,7 @@
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yuzu emulator early access
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=============
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This is the source code for early-access 3275.
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This is the source code for early-access 3276.
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## Legal Notice
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@ -895,45 +895,83 @@ void RasterizerVulkan::UpdateStencilFaces(Tegra::Engines::Maxwell3D::Regs& regs)
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update_compare_masks = true;
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}
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if (update_references) {
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scheduler.Record([front_ref = regs.stencil_front_ref, back_ref = regs.stencil_back_ref,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_ref != back_ref;
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// Front face
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cmdbuf.SetStencilReference(
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set_back ? VK_STENCIL_FACE_FRONT_BIT : VK_STENCIL_FACE_FRONT_AND_BACK, front_ref);
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if (set_back) {
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_BACK_BIT, back_ref);
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilReferenceFront(regs.stencil_front_ref) &&
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!state_tracker.CheckStencilReferenceBack(regs.stencil_back_ref)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilReferenceFront(regs.stencil_front_ref)) {
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return;
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}
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}
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});
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scheduler.Record([front_ref = regs.stencil_front_ref, back_ref = regs.stencil_back_ref,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_ref != back_ref;
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// Front face
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cmdbuf.SetStencilReference(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_ref);
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if (set_back) {
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cmdbuf.SetStencilReference(VK_STENCIL_FACE_BACK_BIT, back_ref);
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}
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});
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}();
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}
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if (update_write_mask) {
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scheduler.Record([front_write_mask = regs.stencil_front_mask,
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back_write_mask = regs.stencil_back_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_write_mask != back_write_mask;
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// Front face
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cmdbuf.SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_write_mask);
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if (set_back) {
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, back_write_mask);
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilWriteMaskFront(regs.stencil_front_mask) &&
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!state_tracker.CheckStencilWriteMaskBack(regs.stencil_back_mask)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilWriteMaskFront(regs.stencil_front_mask)) {
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return;
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}
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}
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});
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scheduler.Record([front_write_mask = regs.stencil_front_mask,
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back_write_mask = regs.stencil_back_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_write_mask != back_write_mask;
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// Front face
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cmdbuf.SetStencilWriteMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_write_mask);
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if (set_back) {
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cmdbuf.SetStencilWriteMask(VK_STENCIL_FACE_BACK_BIT, back_write_mask);
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}
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});
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}();
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}
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if (update_compare_masks) {
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scheduler.Record([front_test_mask = regs.stencil_front_func_mask,
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back_test_mask = regs.stencil_back_func_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_test_mask != back_test_mask;
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// Front face
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cmdbuf.SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_test_mask);
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if (set_back) {
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, back_test_mask);
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[&]() {
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if (regs.stencil_two_side_enable) {
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if (!state_tracker.CheckStencilCompareMaskFront(regs.stencil_front_func_mask) &&
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!state_tracker.CheckStencilCompareMaskBack(regs.stencil_back_func_mask)) {
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return;
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}
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} else {
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if (!state_tracker.CheckStencilCompareMaskFront(regs.stencil_front_func_mask)) {
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return;
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}
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}
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});
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scheduler.Record([front_test_mask = regs.stencil_front_func_mask,
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back_test_mask = regs.stencil_back_func_mask,
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two_sided = regs.stencil_two_side_enable](vk::CommandBuffer cmdbuf) {
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const bool set_back = two_sided && front_test_mask != back_test_mask;
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// Front face
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cmdbuf.SetStencilCompareMask(set_back ? VK_STENCIL_FACE_FRONT_BIT
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: VK_STENCIL_FACE_FRONT_AND_BACK,
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front_test_mask);
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if (set_back) {
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cmdbuf.SetStencilCompareMask(VK_STENCIL_FACE_BACK_BIT, back_test_mask);
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}
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});
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}();
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}
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state_tracker.ClearStencilReset();
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}
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void RasterizerVulkan::UpdateLineWidth(Tegra::Engines::Maxwell3D::Regs& regs) {
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@ -244,9 +244,11 @@ void StateTracker::ChangeChannel(Tegra::Control::ChannelState& channel_state) {
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void StateTracker::InvalidateState() {
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flags->set();
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current_topology = INVALID_TOPOLOGY;
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stencil_reset = true;
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}
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StateTracker::StateTracker()
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: flags{&default_flags}, default_flags{}, invalidation_flags{MakeInvalidationFlags()} {}
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} // namespace Vulkan
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} // namespace Vulkan
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void InvalidateCommandBufferState() {
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(*flags) |= invalidation_flags;
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current_topology = INVALID_TOPOLOGY;
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stencil_reset = true;
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}
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void InvalidateViewports() {
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@ -128,12 +129,45 @@ public:
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return Exchange(Dirty::StencilCompare, false);
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}
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bool TouchStencilSide(bool two_sided_stencil_new) {
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bool result = two_sided_stencil != two_sided_stencil_new;
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two_sided_stencil = two_sided_stencil_new;
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template <typename T>
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bool ExchangeCheck(T& old_value, T new_value) {
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bool result = old_value != new_value;
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old_value = new_value;
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return result;
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}
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bool TouchStencilSide(bool two_sided_stencil_new) {
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return ExchangeCheck(two_sided_stencil, two_sided_stencil_new) || stencil_reset;
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}
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bool CheckStencilReferenceFront(u32 new_value) {
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return ExchangeCheck(front.ref, new_value) || stencil_reset;
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}
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bool CheckStencilReferenceBack(u32 new_value) {
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return ExchangeCheck(back.ref, new_value) || stencil_reset;
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}
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bool CheckStencilWriteMaskFront(u32 new_value) {
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return ExchangeCheck(front.write_mask, new_value) || stencil_reset;
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}
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bool CheckStencilWriteMaskBack(u32 new_value) {
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return ExchangeCheck(back.write_mask, new_value) || stencil_reset;
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}
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bool CheckStencilCompareMaskFront(u32 new_value) {
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return ExchangeCheck(front.compare_mask, new_value) || stencil_reset;
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}
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bool CheckStencilCompareMaskBack(u32 new_value) {
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return ExchangeCheck(back.compare_mask, new_value) || stencil_reset;
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}
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void ClearStencilReset() {
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stencil_reset = false;
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}
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bool TouchLineWidth() const {
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return Exchange(Dirty::LineWidth, false);
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}
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@ -235,11 +269,20 @@ private:
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return is_dirty;
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}
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struct StencilProperties {
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u32 ref = 0;
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u32 write_mask = 0;
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u32 compare_mask = 0;
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};
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Tegra::Engines::Maxwell3D::DirtyState::Flags* flags;
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Tegra::Engines::Maxwell3D::DirtyState::Flags default_flags;
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Tegra::Engines::Maxwell3D::DirtyState::Flags invalidation_flags;
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Maxwell::PrimitiveTopology current_topology = INVALID_TOPOLOGY;
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bool two_sided_stencil = false;
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StencilProperties front{};
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StencilProperties back{};
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bool stencil_reset = false;
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};
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} // namespace Vulkan
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@ -1531,8 +1531,6 @@ void TextureCache<P>::BubbleUpImages(VAddr cpu_addr, size_t size) {
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if (slot_images[bottom_map.image_id].modification_tick <
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slot_images[top_map.image_id].modification_tick) {
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std::swap(map_vector[i - 1], map_vector[i]);
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} else {
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return;
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}
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}
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});
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