shader_ir: Correct parsing of scheduling instructions and correct sizing
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cfb3db1a32
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@ -20,10 +20,10 @@ using Tegra::Shader::OpCode;
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constexpr s32 unassigned_branch = -2;
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constexpr s32 unassigned_branch = -2;
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/***
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/**
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* 'ControlStack' represents a static stack of control jumps such as SSY and PBK
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* 'ControlStack' represents a static stack of control jumps such as SSY and PBK
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* stacks in Maxwell.
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* stacks in Maxwell.
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***/
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**/
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struct ControlStack {
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struct ControlStack {
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static constexpr std::size_t stack_fixed_size = 20;
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static constexpr std::size_t stack_fixed_size = 20;
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std::array<u32, stack_fixed_size> stack{};
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std::array<u32, stack_fixed_size> stack{};
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@ -105,9 +105,11 @@ struct BlockInfo {
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};
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};
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struct CFGRebuildState {
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struct CFGRebuildState {
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explicit CFGRebuildState(const ProgramCode& program_code, const std::size_t program_size)
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explicit CFGRebuildState(const ProgramCode& program_code, const std::size_t program_size,
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: program_code{program_code}, program_size{program_size} {}
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const u32 start)
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: program_code{program_code}, program_size{program_size}, start{start} {}
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u32 start{};
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std::vector<BlockInfo> block_info{};
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std::vector<BlockInfo> block_info{};
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std::list<u32> inspect_queries{};
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std::list<u32> inspect_queries{};
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std::list<Query> queries{};
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std::list<Query> queries{};
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@ -120,7 +122,7 @@ struct CFGRebuildState {
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const std::size_t program_size;
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const std::size_t program_size;
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};
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};
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enum class BlockCollision : u32 { None = 0, Found = 1, Inside = 2 };
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enum class BlockCollision : u32 { None, Found, Inside };
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std::pair<BlockCollision, std::vector<BlockInfo>::iterator> TryGetBlock(CFGRebuildState& state,
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std::pair<BlockCollision, std::vector<BlockInfo>::iterator> TryGetBlock(CFGRebuildState& state,
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u32 address) {
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u32 address) {
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@ -155,15 +157,26 @@ Pred GetPredicate(u32 index, bool negated) {
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return static_cast<Pred>(index + (negated ? 8 : 0));
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return static_cast<Pred>(index + (negated ? 8 : 0));
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}
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}
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/**
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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constexpr u32 SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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enum class ParseResult : u32 {
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enum class ParseResult : u32 {
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ControlCaught = 0,
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ControlCaught,
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BlockEnd = 1,
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BlockEnd,
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AbnormalFlow = 2,
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AbnormalFlow,
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};
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};
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ParseResult ParseCode(CFGRebuildState& state, u32 address, ParseInfo& parse_info) {
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ParseResult ParseCode(CFGRebuildState& state, u32 address, ParseInfo& parse_info) {
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u32 offset = static_cast<u32>(address);
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u32 offset = static_cast<u32>(address);
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const u32 end_address = static_cast<u32>(state.program_size / 8U);
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const u32 end_address = static_cast<u32>(state.program_size / sizeof(Instruction));
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const auto insert_label = ([](CFGRebuildState& state, u32 address) {
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const auto insert_label = ([](CFGRebuildState& state, u32 address) {
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auto pair = state.labels.emplace(address);
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auto pair = state.labels.emplace(address);
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@ -183,6 +196,10 @@ ParseResult ParseCode(CFGRebuildState& state, u32 address, ParseInfo& parse_info
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parse_info.branch_info.ignore = true;
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parse_info.branch_info.ignore = true;
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break;
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break;
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}
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}
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if (IsSchedInstruction(offset, state.start)) {
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offset++;
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continue;
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}
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const Instruction instr = {state.program_code[offset]};
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const Instruction instr = {state.program_code[offset]};
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const auto opcode = OpCode::Decode(instr);
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const auto opcode = OpCode::Decode(instr);
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if (!opcode || opcode->get().GetType() != OpCode::Type::Flow) {
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if (!opcode || opcode->get().GetType() != OpCode::Type::Flow) {
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@ -447,11 +464,11 @@ bool TryQuery(CFGRebuildState& state) {
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std::optional<ShaderCharacteristics> ScanFlow(const ProgramCode& program_code, u32 program_size,
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std::optional<ShaderCharacteristics> ScanFlow(const ProgramCode& program_code, u32 program_size,
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u32 start_address) {
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u32 start_address) {
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CFGRebuildState state{program_code, program_size};
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CFGRebuildState state{program_code, program_size, start_address};
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// Inspect Code and generate blocks
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// Inspect Code and generate blocks
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state.labels.clear();
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state.labels.clear();
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state.labels.emplace(start_address);
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state.labels.emplace(start_address);
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state.inspect_queries.push_back(start_address);
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state.inspect_queries.push_back(state.start);
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while (!state.inspect_queries.empty()) {
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while (!state.inspect_queries.empty()) {
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if (!TryInspectAddress(state)) {
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if (!TryInspectAddress(state)) {
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return {};
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return {};
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@ -459,7 +476,7 @@ std::optional<ShaderCharacteristics> ScanFlow(const ProgramCode& program_code, u
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}
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}
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// Decompile Stacks
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// Decompile Stacks
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Query start_query{};
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Query start_query{};
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start_query.address = start_address;
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start_query.address = state.start;
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state.queries.push_back(start_query);
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state.queries.push_back(start_query);
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bool decompiled = true;
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bool decompiled = true;
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while (!state.queries.empty()) {
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while (!state.queries.empty()) {
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@ -39,7 +39,7 @@ void ShaderIR::Decode() {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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disable_flow_stack = false;
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disable_flow_stack = false;
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const auto info = ScanFlow(program_code, program_size, main_offset);
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const auto info = ScanFlow(program_code, MAX_PROGRAM_LENGTH * sizeof(u64), main_offset);
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if (info) {
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if (info) {
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const auto& shader_info = *info;
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const auto& shader_info = *info;
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coverage_begin = shader_info.start;
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coverage_begin = shader_info.start;
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