Merge pull request #387 from Subv/maxwell_2d
GPU: Partially implemented the 2D surface copy engine
This commit is contained in:
bunnei
GitHub
commit
42d43ea741
@ -659,6 +659,10 @@ void CopyBlock(const Kernel::Process& process, VAddr dest_addr, VAddr src_addr,
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}
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}
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void CopyBlock(VAddr dest_addr, VAddr src_addr, size_t size) {
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CopyBlock(*Core::CurrentProcess(), dest_addr, src_addr, size);
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}
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boost::optional<PAddr> TryVirtualToPhysicalAddress(const VAddr addr) {
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if (addr == 0) {
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return 0;
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@ -24,10 +24,7 @@ namespace Tegra {
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enum class BufferMethods {
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BindObject = 0,
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SetGraphMacroCode = 0x45,
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SetGraphMacroCodeArg = 0x46,
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SetGraphMacroEntry = 0x47,
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CountBufferMethods = 0x100,
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CountBufferMethods = 0x40,
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};
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void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params) {
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@ -36,28 +33,6 @@ void GPU::WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params)
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"{:08X} remaining params {}",
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method, subchannel, value, remaining_params);
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if (method == static_cast<u32>(BufferMethods::SetGraphMacroEntry)) {
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// Prepare to upload a new macro, reset the upload counter.
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NGLOG_DEBUG(HW_GPU, "Uploading GPU macro {:08X}", value);
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current_macro_entry = value;
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current_macro_code.clear();
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return;
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}
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if (method == static_cast<u32>(BufferMethods::SetGraphMacroCodeArg)) {
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// Append a new code word to the current macro.
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current_macro_code.push_back(value);
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// There are no more params remaining, submit the code to the 3D engine.
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if (remaining_params == 0) {
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maxwell_3d->SubmitMacroCode(current_macro_entry, std::move(current_macro_code));
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current_macro_entry = InvalidGraphMacroEntry;
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current_macro_code.clear();
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}
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return;
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}
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if (method == static_cast<u32>(BufferMethods::BindObject)) {
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// Bind the current subchannel to the desired engine id.
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NGLOG_DEBUG(HW_GPU, "Binding subchannel {} to engine {}", subchannel, value);
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@ -2,12 +2,71 @@
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "core/memory.h"
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#include "video_core/engines/fermi_2d.h"
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#include "video_core/textures/decoders.h"
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namespace Tegra {
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namespace Engines {
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void Fermi2D::WriteReg(u32 method, u32 value) {}
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Fermi2D::Fermi2D(MemoryManager& memory_manager) : memory_manager(memory_manager) {}
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void Fermi2D::WriteReg(u32 method, u32 value) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Fermi2D register, increase the size of the Regs structure");
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regs.reg_array[method] = value;
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switch (method) {
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case FERMI2D_REG_INDEX(trigger): {
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HandleSurfaceCopy();
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break;
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}
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}
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}
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void Fermi2D::HandleSurfaceCopy() {
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NGLOG_WARNING(HW_GPU, "Requested a surface copy with operation {}",
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static_cast<u32>(regs.operation));
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const GPUVAddr source = regs.src.Address();
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const GPUVAddr dest = regs.dst.Address();
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// TODO(Subv): Only same-format and same-size copies are allowed for now.
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ASSERT(regs.src.format == regs.dst.format);
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ASSERT(regs.src.width * regs.src.height == regs.dst.width * regs.dst.height);
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// TODO(Subv): Only raw copies are implemented.
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ASSERT(regs.operation == Regs::Operation::SrcCopy);
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const VAddr source_cpu = *memory_manager.GpuToCpuAddress(source);
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const VAddr dest_cpu = *memory_manager.GpuToCpuAddress(dest);
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u32 src_bytes_per_pixel = RenderTargetBytesPerPixel(regs.src.format);
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u32 dst_bytes_per_pixel = RenderTargetBytesPerPixel(regs.dst.format);
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if (regs.src.linear == regs.dst.linear) {
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// If the input layout and the output layout are the same, just perform a raw copy.
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Memory::CopyBlock(dest_cpu, source_cpu,
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src_bytes_per_pixel * regs.dst.width * regs.dst.height);
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return;
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}
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u8* src_buffer = Memory::GetPointer(source_cpu);
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u8* dst_buffer = Memory::GetPointer(dest_cpu);
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if (!regs.src.linear && regs.dst.linear) {
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// If the input is tiled and the output is linear, deswizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
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dst_bytes_per_pixel, src_buffer, dst_buffer, true,
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regs.src.block_height);
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} else {
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// If the input is linear and the output is tiled, swizzle the input and copy it over.
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Texture::CopySwizzledData(regs.src.width, regs.src.height, src_bytes_per_pixel,
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dst_bytes_per_pixel, dst_buffer, src_buffer, false,
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regs.dst.block_height);
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}
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}
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} // namespace Engines
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} // namespace Tegra
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@ -4,19 +4,106 @@
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#pragma once
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#include <array>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "video_core/gpu.h"
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#include "video_core/memory_manager.h"
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namespace Tegra {
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namespace Engines {
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#define FERMI2D_REG_INDEX(field_name) \
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(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
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class Fermi2D final {
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public:
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Fermi2D() = default;
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explicit Fermi2D(MemoryManager& memory_manager);
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~Fermi2D() = default;
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value);
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struct Regs {
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static constexpr size_t NUM_REGS = 0x258;
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struct Surface {
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RenderTargetFormat format;
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BitField<0, 1, u32> linear;
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union {
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BitField<0, 4, u32> block_depth;
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BitField<4, 4, u32> block_height;
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BitField<8, 4, u32> block_width;
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};
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u32 depth;
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u32 layer;
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u32 pitch;
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u32 width;
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u32 height;
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u32 address_high;
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u32 address_low;
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GPUVAddr Address() const {
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return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
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address_low);
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}
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};
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static_assert(sizeof(Surface) == 0x28, "Surface has incorrect size");
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enum class Operation : u32 {
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SrcCopyAnd = 0,
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ROPAnd = 1,
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Blend = 2,
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SrcCopy = 3,
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ROP = 4,
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SrcCopyPremult = 5,
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BlendPremult = 6,
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};
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union {
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struct {
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INSERT_PADDING_WORDS(0x80);
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Surface dst;
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INSERT_PADDING_WORDS(2);
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Surface src;
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INSERT_PADDING_WORDS(0x15);
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Operation operation;
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INSERT_PADDING_WORDS(0x9);
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// TODO(Subv): This is only a guess.
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u32 trigger;
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INSERT_PADDING_WORDS(0x1A3);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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} regs{};
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MemoryManager& memory_manager;
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private:
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/// Performs the copy from the source surface to the destination surface as configured in the
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/// registers.
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void HandleSurfaceCopy();
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};
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Fermi2D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(dst, 0x80);
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ASSERT_REG_POSITION(src, 0x8C);
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ASSERT_REG_POSITION(operation, 0xAB);
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ASSERT_REG_POSITION(trigger, 0xB5);
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#undef ASSERT_REG_POSITION
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} // namespace Engines
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} // namespace Tegra
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@ -22,10 +22,6 @@ constexpr u32 MacroRegistersStart = 0xE00;
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Maxwell3D::Maxwell3D(MemoryManager& memory_manager)
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: memory_manager(memory_manager), macro_interpreter(*this) {}
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void Maxwell3D::SubmitMacroCode(u32 entry, std::vector<u32> code) {
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uploaded_macros[entry * 2 + MacroRegistersStart] = std::move(code);
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}
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void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
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auto macro_code = uploaded_macros.find(method);
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// The requested macro must have been uploaded already.
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@ -37,9 +33,6 @@ void Maxwell3D::CallMacroMethod(u32 method, std::vector<u32> parameters) {
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}
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void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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auto debug_context = Core::System::GetInstance().GetGPUDebugContext();
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// It is an error to write to a register other than the current macro's ARG register before it
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@ -68,6 +61,9 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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return;
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}
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ASSERT_MSG(method < Regs::NUM_REGS,
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"Invalid Maxwell3D register, increase the size of the Regs structure");
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if (debug_context) {
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debug_context->OnEvent(Tegra::DebugContext::Event::MaxwellCommandLoaded, nullptr);
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}
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@ -75,6 +71,10 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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regs.reg_array[method] = value;
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switch (method) {
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case MAXWELL3D_REG_INDEX(macros.data): {
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ProcessMacroUpload(value);
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break;
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}
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case MAXWELL3D_REG_INDEX(code_address.code_address_high):
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case MAXWELL3D_REG_INDEX(code_address.code_address_low): {
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// Note: For some reason games (like Puyo Puyo Tetris) seem to write 0 to the CODE_ADDRESS
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@ -141,6 +141,12 @@ void Maxwell3D::WriteReg(u32 method, u32 value, u32 remaining_params) {
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}
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}
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void Maxwell3D::ProcessMacroUpload(u32 data) {
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// Store the uploaded macro code to interpret them when they're called.
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auto& macro = uploaded_macros[regs.macros.entry * 2 + MacroRegistersStart];
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macro.push_back(data);
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}
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void Maxwell3D::ProcessQueryGet() {
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GPUVAddr sequence_address = regs.query.QueryAddress();
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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@ -31,7 +31,7 @@ public:
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/// Register structure of the Maxwell3D engine.
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/// TODO(Subv): This structure will need to be made bigger as more registers are discovered.
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struct Regs {
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static constexpr size_t NUM_REGS = 0xE36;
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static constexpr size_t NUM_REGS = 0xE00;
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static constexpr size_t NumRenderTargets = 8;
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static constexpr size_t NumViewports = 16;
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@ -322,7 +322,15 @@ public:
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union {
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struct {
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INSERT_PADDING_WORDS(0x200);
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INSERT_PADDING_WORDS(0x45);
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struct {
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INSERT_PADDING_WORDS(1);
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u32 data;
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u32 entry;
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} macros;
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INSERT_PADDING_WORDS(0x1B8);
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struct {
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u32 address_high;
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@ -605,7 +613,7 @@ public:
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u32 size[MaxShaderStage];
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} tex_info_buffers;
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INSERT_PADDING_WORDS(0x102);
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INSERT_PADDING_WORDS(0xCC);
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};
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std::array<u32, NUM_REGS> reg_array;
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};
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@ -637,9 +645,6 @@ public:
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/// Write the value to the register identified by method.
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void WriteReg(u32 method, u32 value, u32 remaining_params);
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/// Uploads the code for a GPU macro program associated with the specified entry.
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void SubmitMacroCode(u32 entry, std::vector<u32> code);
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/// Returns a list of enabled textures for the specified shader stage.
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std::vector<Texture::FullTextureInfo> GetStageTextures(Regs::ShaderStage stage) const;
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@ -670,6 +675,9 @@ private:
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*/
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void CallMacroMethod(u32 method, std::vector<u32> parameters);
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/// Handles writes to the macro uploading registers.
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void ProcessMacroUpload(u32 data);
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/// Handles a write to the QUERY_GET register.
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void ProcessQueryGet();
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@ -687,6 +695,7 @@ private:
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static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(macros, 0x45);
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ASSERT_REG_POSITION(rt, 0x200);
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ASSERT_REG_POSITION(viewport_transform[0], 0x280);
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ASSERT_REG_POSITION(viewport, 0x300);
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@ -12,7 +12,7 @@ namespace Tegra {
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GPU::GPU() {
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memory_manager = std::make_unique<MemoryManager>();
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maxwell_3d = std::make_unique<Engines::Maxwell3D>(*memory_manager);
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fermi_2d = std::make_unique<Engines::Fermi2D>();
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fermi_2d = std::make_unique<Engines::Fermi2D>(*memory_manager);
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maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
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}
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@ -22,4 +22,16 @@ const Tegra::Engines::Maxwell3D& GPU::Get3DEngine() const {
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return *maxwell_3d;
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}
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u32 RenderTargetBytesPerPixel(RenderTargetFormat format) {
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ASSERT(format != RenderTargetFormat::NONE);
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switch (format) {
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case RenderTargetFormat::RGBA8_UNORM:
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case RenderTargetFormat::RGB10_A2_UNORM:
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return 4;
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default:
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UNIMPLEMENTED_MSG("Unimplemented render target format %u", static_cast<u32>(format));
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}
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}
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} // namespace Tegra
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@ -21,6 +21,9 @@ enum class RenderTargetFormat : u32 {
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RGBA8_SRGB = 0xD6,
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};
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/// Returns the number of bytes per pixel of each rendertarget format.
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u32 RenderTargetBytesPerPixel(RenderTargetFormat format);
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class DebugContext;
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/**
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@ -86,8 +89,6 @@ public:
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}
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private:
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static constexpr u32 InvalidGraphMacroEntry = 0xFFFFFFFF;
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/// Writes a single register in the engine bound to the specified subchannel
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void WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params);
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@ -100,11 +101,6 @@ private:
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std::unique_ptr<Engines::Fermi2D> fermi_2d;
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/// Compute engine
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std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
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/// Entry of the macro that is currently being uploaded
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u32 current_macro_entry = InvalidGraphMacroEntry;
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/// Code being uploaded for the current macro
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std::vector<u32> current_macro_code;
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};
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} // namespace Tegra
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@ -27,9 +27,8 @@ static u32 GetSwizzleOffset(u32 x, u32 y, u32 image_width, u32 bytes_per_pixel,
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return address;
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}
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static void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
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u8* swizzled_data, u8* unswizzled_data, bool unswizzle,
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u32 block_height) {
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void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
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u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height) {
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u8* data_ptrs[2];
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for (unsigned y = 0; y < height; ++y) {
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for (unsigned x = 0; x < width; ++x) {
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@ -17,6 +17,10 @@ namespace Texture {
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std::vector<u8> UnswizzleTexture(VAddr address, TextureFormat format, u32 width, u32 height,
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u32 block_height = TICEntry::DefaultBlockHeight);
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/// Copies texture data from a buffer and performs swizzling/unswizzling as necessary.
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void CopySwizzledData(u32 width, u32 height, u32 bytes_per_pixel, u32 out_bytes_per_pixel,
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u8* swizzled_data, u8* unswizzled_data, bool unswizzle, u32 block_height);
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/**
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* Decodes an unswizzled texture into a A8R8G8B8 texture.
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*/
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