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arm: dynarmic: Implement icache op handling for 'ic ivau' instruction

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This commit is contained in:
jam1garner 2021-11-21 21:10:14 -05:00
parent d20f91da11
commit 84eb3e7d02
1 changed files with 18 additions and 0 deletions
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18
src/core/arm/dynarmic/arm_dynarmic_64.cpp
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@ -86,6 +86,24 @@ public:
num_instructions, MemoryReadCode(pc));
}
void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
VAddr value) override {
constexpr u64 ICACHE_LINE_SIZE = 64;
u64 cache_line_start;
switch (op) {
case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
return;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
}
}
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
switch (exception) {
case Dynarmic::A64::Exception::WaitForInterrupt: