Merge pull request #2824 from ReinUsesLisp/mme
Revert "Revert #2466" and stub FirmwareCall 4
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commit
b8b1747704
@ -329,6 +329,10 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
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ProcessMacroBind(method_call.argument);
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ProcessMacroBind(method_call.argument);
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break;
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break;
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}
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}
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case MAXWELL3D_REG_INDEX(firmware[4]): {
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ProcessFirmwareCall4();
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break;
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}
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[0]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[0]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[1]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[1]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[2]):
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case MAXWELL3D_REG_INDEX(const_buffer.cb_data[2]):
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@ -419,6 +423,14 @@ void Maxwell3D::ProcessMacroBind(u32 data) {
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macro_positions[regs.macros.entry++] = data;
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macro_positions[regs.macros.entry++] = data;
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}
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}
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void Maxwell3D::ProcessFirmwareCall4() {
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LOG_WARNING(HW_GPU, "(STUBBED) called");
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// Firmware call 4 is a blob that changes some registers depending on its parameters.
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// These registers don't affect emulation and so are stubbed by setting 0xd00 to 1.
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regs.reg_array[0xd00] = 1;
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}
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void Maxwell3D::ProcessQueryGet() {
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void Maxwell3D::ProcessQueryGet() {
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const GPUVAddr sequence_address{regs.query.QueryAddress()};
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const GPUVAddr sequence_address{regs.query.QueryAddress()};
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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// Since the sequence address is given as a GPU VAddr, we have to convert it to an application
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@ -1089,7 +1089,9 @@ public:
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INSERT_PADDING_WORDS(14);
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INSERT_PADDING_WORDS(14);
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} shader_config[MaxShaderProgram];
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} shader_config[MaxShaderProgram];
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INSERT_PADDING_WORDS(0x80);
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INSERT_PADDING_WORDS(0x60);
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u32 firmware[0x20];
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struct {
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struct {
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u32 cb_size;
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u32 cb_size;
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@ -1319,6 +1321,9 @@ private:
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/// Handles writes to the macro bind register.
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/// Handles writes to the macro bind register.
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void ProcessMacroBind(u32 data);
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void ProcessMacroBind(u32 data);
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/// Handles firmware blob 4
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void ProcessFirmwareCall4();
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/// Handles a write to the CLEAR_BUFFERS register.
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/// Handles a write to the CLEAR_BUFFERS register.
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void ProcessClearBuffers();
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void ProcessClearBuffers();
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@ -1431,6 +1436,7 @@ ASSERT_REG_POSITION(vertex_array[0], 0x700);
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ASSERT_REG_POSITION(independent_blend, 0x780);
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ASSERT_REG_POSITION(independent_blend, 0x780);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(vertex_array_limit[0], 0x7C0);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(shader_config[0], 0x800);
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ASSERT_REG_POSITION(firmware, 0x8C0);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(const_buffer, 0x8E0);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(cb_bind[0], 0x904);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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ASSERT_REG_POSITION(tex_cb_index, 0x982);
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@ -131,9 +131,7 @@ bool MacroInterpreter::Step(u32 offset, bool is_delay_slot) {
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// An instruction with the Exit flag will not actually
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// An instruction with the Exit flag will not actually
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// cause an exit if it's executed inside a delay slot.
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// cause an exit if it's executed inside a delay slot.
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// TODO(Blinkhawk): Reversed to always exit. The behavior explained above requires further
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if (opcode.is_exit && !is_delay_slot) {
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// testing on the MME code.
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if (opcode.is_exit) {
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// Exit has a delay slot, execute the next instruction
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// Exit has a delay slot, execute the next instruction
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Step(offset, true);
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Step(offset, true);
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return false;
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return false;
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