dmnt_cheat_vm: Make use of designated initializers
Allows for more compact code.
This commit is contained in:
Lioncash
parent
05781ce8c4
commit
c883666045
@ -313,30 +313,32 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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switch (opcode_type) {
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case CheatVmOpcodeType::StoreStatic: {
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StoreStaticOpcode store_static{};
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// 0TMR00AA AAAAAAAA YYYYYYYY (YYYYYYYY)
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// Read additional words.
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const u32 second_dword = GetNextDword();
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store_static.bit_width = (first_dword >> 24) & 0xF;
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store_static.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF);
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store_static.offset_register = ((first_dword >> 16) & 0xF);
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store_static.rel_address =
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(static_cast<u64>(first_dword & 0xFF) << 32ul) | static_cast<u64>(second_dword);
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store_static.value = GetNextVmInt(store_static.bit_width);
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opcode.opcode = store_static;
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const u32 bit_width = (first_dword >> 24) & 0xF;
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opcode.opcode = StoreStaticOpcode{
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.bit_width = bit_width,
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.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF),
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.offset_register = (first_dword >> 16) & 0xF,
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.rel_address = (static_cast<u64>(first_dword & 0xFF) << 32) | second_dword,
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.value = GetNextVmInt(bit_width),
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};
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} break;
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case CheatVmOpcodeType::BeginConditionalBlock: {
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BeginConditionalOpcode begin_cond{};
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// 1TMC00AA AAAAAAAA YYYYYYYY (YYYYYYYY)
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// Read additional words.
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const u32 second_dword = GetNextDword();
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begin_cond.bit_width = (first_dword >> 24) & 0xF;
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begin_cond.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF);
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begin_cond.cond_type = static_cast<ConditionalComparisonType>((first_dword >> 16) & 0xF);
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begin_cond.rel_address =
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(static_cast<u64>(first_dword & 0xFF) << 32ul) | static_cast<u64>(second_dword);
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begin_cond.value = GetNextVmInt(begin_cond.bit_width);
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opcode.opcode = begin_cond;
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const u32 bit_width = (first_dword >> 24) & 0xF;
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opcode.opcode = BeginConditionalOpcode{
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.bit_width = bit_width,
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.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF),
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.cond_type = static_cast<ConditionalComparisonType>((first_dword >> 16) & 0xF),
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.rel_address = (static_cast<u64>(first_dword & 0xFF) << 32) | second_dword,
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.value = GetNextVmInt(bit_width),
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};
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} break;
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case CheatVmOpcodeType::EndConditionalBlock: {
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// 20000000
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@ -344,12 +346,14 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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opcode.opcode = EndConditionalOpcode{};
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} break;
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case CheatVmOpcodeType::ControlLoop: {
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ControlLoopOpcode ctrl_loop{};
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// 300R0000 VVVVVVVV
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// 310R0000
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// Parse register, whether loop start or loop end.
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ctrl_loop.start_loop = ((first_dword >> 24) & 0xF) == 0;
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ctrl_loop.reg_index = ((first_dword >> 20) & 0xF);
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ControlLoopOpcode ctrl_loop{
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.start_loop = ((first_dword >> 24) & 0xF) == 0,
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.reg_index = (first_dword >> 20) & 0xF,
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.num_iters = 0,
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};
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// Read number of iters if loop start.
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if (ctrl_loop.start_loop) {
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@ -358,66 +362,65 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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opcode.opcode = ctrl_loop;
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} break;
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case CheatVmOpcodeType::LoadRegisterStatic: {
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LoadRegisterStaticOpcode ldr_static{};
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// 400R0000 VVVVVVVV VVVVVVVV
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// Read additional words.
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ldr_static.reg_index = ((first_dword >> 16) & 0xF);
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ldr_static.value =
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(static_cast<u64>(GetNextDword()) << 32ul) | static_cast<u64>(GetNextDword());
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opcode.opcode = ldr_static;
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opcode.opcode = LoadRegisterStaticOpcode{
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.reg_index = (first_dword >> 16) & 0xF,
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.value = (static_cast<u64>(GetNextDword()) << 32) | GetNextDword(),
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};
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} break;
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case CheatVmOpcodeType::LoadRegisterMemory: {
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LoadRegisterMemoryOpcode ldr_memory{};
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// 5TMRI0AA AAAAAAAA
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// Read additional words.
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const u32 second_dword = GetNextDword();
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ldr_memory.bit_width = (first_dword >> 24) & 0xF;
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ldr_memory.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF);
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ldr_memory.reg_index = ((first_dword >> 16) & 0xF);
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ldr_memory.load_from_reg = ((first_dword >> 12) & 0xF) != 0;
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ldr_memory.rel_address =
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(static_cast<u64>(first_dword & 0xFF) << 32ul) | static_cast<u64>(second_dword);
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opcode.opcode = ldr_memory;
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opcode.opcode = LoadRegisterMemoryOpcode{
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.bit_width = (first_dword >> 24) & 0xF,
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.mem_type = static_cast<MemoryAccessType>((first_dword >> 20) & 0xF),
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.reg_index = ((first_dword >> 16) & 0xF),
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.load_from_reg = ((first_dword >> 12) & 0xF) != 0,
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.rel_address = (static_cast<u64>(first_dword & 0xFF) << 32) | second_dword,
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};
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} break;
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case CheatVmOpcodeType::StoreStaticToAddress: {
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StoreStaticToAddressOpcode str_static{};
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// 6T0RIor0 VVVVVVVV VVVVVVVV
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// Read additional words.
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str_static.bit_width = (first_dword >> 24) & 0xF;
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str_static.reg_index = ((first_dword >> 16) & 0xF);
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str_static.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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str_static.add_offset_reg = ((first_dword >> 8) & 0xF) != 0;
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str_static.offset_reg_index = ((first_dword >> 4) & 0xF);
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str_static.value =
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(static_cast<u64>(GetNextDword()) << 32ul) | static_cast<u64>(GetNextDword());
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opcode.opcode = str_static;
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opcode.opcode = StoreStaticToAddressOpcode{
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.bit_width = (first_dword >> 24) & 0xF,
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.reg_index = (first_dword >> 16) & 0xF,
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.increment_reg = ((first_dword >> 12) & 0xF) != 0,
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.add_offset_reg = ((first_dword >> 8) & 0xF) != 0,
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.offset_reg_index = (first_dword >> 4) & 0xF,
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.value = (static_cast<u64>(GetNextDword()) << 32) | GetNextDword(),
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};
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} break;
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case CheatVmOpcodeType::PerformArithmeticStatic: {
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PerformArithmeticStaticOpcode perform_math_static{};
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// 7T0RC000 VVVVVVVV
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// Read additional words.
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perform_math_static.bit_width = (first_dword >> 24) & 0xF;
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perform_math_static.reg_index = ((first_dword >> 16) & 0xF);
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perform_math_static.math_type =
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static_cast<RegisterArithmeticType>((first_dword >> 12) & 0xF);
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perform_math_static.value = GetNextDword();
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opcode.opcode = perform_math_static;
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opcode.opcode = PerformArithmeticStaticOpcode{
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.bit_width = (first_dword >> 24) & 0xF,
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.reg_index = ((first_dword >> 16) & 0xF),
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.math_type = static_cast<RegisterArithmeticType>((first_dword >> 12) & 0xF),
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.value = GetNextDword(),
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};
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} break;
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case CheatVmOpcodeType::BeginKeypressConditionalBlock: {
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BeginKeypressConditionalOpcode begin_keypress_cond{};
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// 8kkkkkkk
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// Just parse the mask.
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begin_keypress_cond.key_mask = first_dword & 0x0FFFFFFF;
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opcode.opcode = begin_keypress_cond;
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opcode.opcode = BeginKeypressConditionalOpcode{
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.key_mask = first_dword & 0x0FFFFFFF,
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};
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} break;
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case CheatVmOpcodeType::PerformArithmeticRegister: {
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PerformArithmeticRegisterOpcode perform_math_reg{};
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// 9TCRSIs0 (VVVVVVVV (VVVVVVVV))
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perform_math_reg.bit_width = (first_dword >> 24) & 0xF;
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perform_math_reg.math_type = static_cast<RegisterArithmeticType>((first_dword >> 20) & 0xF);
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perform_math_reg.dst_reg_index = ((first_dword >> 16) & 0xF);
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perform_math_reg.src_reg_1_index = ((first_dword >> 12) & 0xF);
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perform_math_reg.has_immediate = ((first_dword >> 8) & 0xF) != 0;
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PerformArithmeticRegisterOpcode perform_math_reg{
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.bit_width = (first_dword >> 24) & 0xF,
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.math_type = static_cast<RegisterArithmeticType>((first_dword >> 20) & 0xF),
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.dst_reg_index = (first_dword >> 16) & 0xF,
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.src_reg_1_index = (first_dword >> 12) & 0xF,
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.src_reg_2_index = 0,
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.has_immediate = ((first_dword >> 8) & 0xF) != 0,
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.value = {},
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};
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if (perform_math_reg.has_immediate) {
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perform_math_reg.src_reg_2_index = 0;
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perform_math_reg.value = GetNextVmInt(perform_math_reg.bit_width);
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@ -427,7 +430,6 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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opcode.opcode = perform_math_reg;
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} break;
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case CheatVmOpcodeType::StoreRegisterToAddress: {
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StoreRegisterToAddressOpcode str_register{};
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// ATSRIOxa (aaaaaaaa)
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// A = opcode 10
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// T = bit width
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@ -439,20 +441,23 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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// Relative Address
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// x = offset register (for offset type 1), memory type (for offset type 3)
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// a = relative address (for offset type 2+3)
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str_register.bit_width = (first_dword >> 24) & 0xF;
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str_register.str_reg_index = ((first_dword >> 20) & 0xF);
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str_register.addr_reg_index = ((first_dword >> 16) & 0xF);
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str_register.increment_reg = ((first_dword >> 12) & 0xF) != 0;
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str_register.ofs_type = static_cast<StoreRegisterOffsetType>(((first_dword >> 8) & 0xF));
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str_register.ofs_reg_index = ((first_dword >> 4) & 0xF);
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StoreRegisterToAddressOpcode str_register{
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.bit_width = (first_dword >> 24) & 0xF,
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.str_reg_index = (first_dword >> 20) & 0xF,
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.addr_reg_index = (first_dword >> 16) & 0xF,
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.increment_reg = ((first_dword >> 12) & 0xF) != 0,
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.ofs_type = static_cast<StoreRegisterOffsetType>(((first_dword >> 8) & 0xF)),
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.mem_type = MemoryAccessType::MainNso,
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.ofs_reg_index = (first_dword >> 4) & 0xF,
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.rel_address = 0,
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};
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switch (str_register.ofs_type) {
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case StoreRegisterOffsetType::None:
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case StoreRegisterOffsetType::Reg:
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// Nothing more to do
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break;
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case StoreRegisterOffsetType::Imm:
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str_register.rel_address =
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((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
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str_register.rel_address = (static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
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break;
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case StoreRegisterOffsetType::MemReg:
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str_register.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
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@ -460,8 +465,7 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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case StoreRegisterOffsetType::MemImm:
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case StoreRegisterOffsetType::MemImmReg:
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str_register.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
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str_register.rel_address =
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((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
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str_register.rel_address = (static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
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break;
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default:
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str_register.ofs_type = StoreRegisterOffsetType::None;
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@ -470,7 +474,6 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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opcode.opcode = str_register;
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} break;
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case CheatVmOpcodeType::BeginRegisterConditionalBlock: {
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BeginRegisterConditionalOpcode begin_reg_cond{};
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// C0TcSX##
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// C0TcS0Ma aaaaaaaa
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// C0TcS1Mr
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@ -492,11 +495,19 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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// r = offset register.
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// X = other register.
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// V = value.
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begin_reg_cond.bit_width = (first_dword >> 20) & 0xF;
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begin_reg_cond.cond_type =
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static_cast<ConditionalComparisonType>((first_dword >> 16) & 0xF);
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begin_reg_cond.val_reg_index = ((first_dword >> 12) & 0xF);
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begin_reg_cond.comp_type = static_cast<CompareRegisterValueType>((first_dword >> 8) & 0xF);
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BeginRegisterConditionalOpcode begin_reg_cond{
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.bit_width = (first_dword >> 20) & 0xF,
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.cond_type = static_cast<ConditionalComparisonType>((first_dword >> 16) & 0xF),
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.val_reg_index = (first_dword >> 12) & 0xF,
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.comp_type = static_cast<CompareRegisterValueType>((first_dword >> 8) & 0xF),
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.mem_type = MemoryAccessType::MainNso,
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.addr_reg_index = 0,
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.other_reg_index = 0,
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.ofs_reg_index = 0,
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.rel_address = 0,
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.value = {},
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};
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switch (begin_reg_cond.comp_type) {
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case CompareRegisterValueType::StaticValue:
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@ -508,26 +519,25 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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case CompareRegisterValueType::MemoryRelAddr:
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begin_reg_cond.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
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begin_reg_cond.rel_address =
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((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
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(static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
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break;
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case CompareRegisterValueType::MemoryOfsReg:
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begin_reg_cond.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
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begin_reg_cond.ofs_reg_index = (first_dword & 0xF);
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break;
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case CompareRegisterValueType::RegisterRelAddr:
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begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF);
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begin_reg_cond.addr_reg_index = (first_dword >> 4) & 0xF;
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begin_reg_cond.rel_address =
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((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
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(static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
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break;
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case CompareRegisterValueType::RegisterOfsReg:
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begin_reg_cond.addr_reg_index = ((first_dword >> 4) & 0xF);
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begin_reg_cond.ofs_reg_index = (first_dword & 0xF);
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begin_reg_cond.addr_reg_index = (first_dword >> 4) & 0xF;
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begin_reg_cond.ofs_reg_index = first_dword & 0xF;
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break;
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}
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opcode.opcode = begin_reg_cond;
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} break;
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case CheatVmOpcodeType::SaveRestoreRegister: {
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SaveRestoreRegisterOpcode save_restore_reg{};
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// C10D0Sx0
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// C1 = opcode 0xC1
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// D = destination index.
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@ -535,36 +545,37 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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// x = 3 if clearing reg, 2 if clearing saved value, 1 if saving a register, 0 if restoring
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// a register.
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// NOTE: If we add more save slots later, current encoding is backwards compatible.
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save_restore_reg.dst_index = (first_dword >> 16) & 0xF;
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save_restore_reg.src_index = (first_dword >> 8) & 0xF;
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save_restore_reg.op_type = static_cast<SaveRestoreRegisterOpType>((first_dword >> 4) & 0xF);
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opcode.opcode = save_restore_reg;
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opcode.opcode = SaveRestoreRegisterOpcode{
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.dst_index = (first_dword >> 16) & 0xF,
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.src_index = (first_dword >> 8) & 0xF,
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.op_type = static_cast<SaveRestoreRegisterOpType>((first_dword >> 4) & 0xF),
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};
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} break;
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case CheatVmOpcodeType::SaveRestoreRegisterMask: {
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SaveRestoreRegisterMaskOpcode save_restore_regmask{};
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// C2x0XXXX
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// C2 = opcode 0xC2
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// x = 3 if clearing reg, 2 if clearing saved value, 1 if saving, 0 if restoring.
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// X = 16-bit bitmask, bit i --> save or restore register i.
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save_restore_regmask.op_type =
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static_cast<SaveRestoreRegisterOpType>((first_dword >> 20) & 0xF);
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SaveRestoreRegisterMaskOpcode save_restore_regmask{
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.op_type = static_cast<SaveRestoreRegisterOpType>((first_dword >> 20) & 0xF),
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.should_operate = {},
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};
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for (std::size_t i = 0; i < NumRegisters; i++) {
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save_restore_regmask.should_operate[i] = (first_dword & (1u << i)) != 0;
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save_restore_regmask.should_operate[i] = (first_dword & (1U << i)) != 0;
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}
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opcode.opcode = save_restore_regmask;
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} break;
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case CheatVmOpcodeType::ReadWriteStaticRegister: {
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ReadWriteStaticRegisterOpcode rw_static_reg{};
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// C3000XXx
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// C3 = opcode 0xC3.
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// XX = static register index.
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// x = register index.
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rw_static_reg.static_idx = ((first_dword >> 4) & 0xFF);
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rw_static_reg.idx = (first_dword & 0xF);
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opcode.opcode = rw_static_reg;
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opcode.opcode = ReadWriteStaticRegisterOpcode{
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.static_idx = (first_dword >> 4) & 0xFF,
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.idx = first_dword & 0xF,
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};
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} break;
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case CheatVmOpcodeType::DebugLog: {
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DebugLogOpcode debug_log{};
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// FFFTIX##
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// FFFTI0Ma aaaaaaaa
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// FFFTI1Mr
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@ -583,31 +594,36 @@ bool DmntCheatVm::DecodeNextOpcode(CheatVmOpcode& out) {
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// a = relative address.
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// r = offset register.
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// X = value register.
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debug_log.bit_width = (first_dword >> 16) & 0xF;
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debug_log.log_id = ((first_dword >> 12) & 0xF);
|
||||
debug_log.val_type = static_cast<DebugLogValueType>((first_dword >> 8) & 0xF);
|
||||
DebugLogOpcode debug_log{
|
||||
.bit_width = (first_dword >> 16) & 0xF,
|
||||
.log_id = (first_dword >> 12) & 0xF,
|
||||
.val_type = static_cast<DebugLogValueType>((first_dword >> 8) & 0xF),
|
||||
.mem_type = MemoryAccessType::MainNso,
|
||||
.addr_reg_index = 0,
|
||||
.val_reg_index = 0,
|
||||
.ofs_reg_index = 0,
|
||||
.rel_address = 0,
|
||||
};
|
||||
|
||||
switch (debug_log.val_type) {
|
||||
case DebugLogValueType::RegisterValue:
|
||||
debug_log.val_reg_index = ((first_dword >> 4) & 0xF);
|
||||
debug_log.val_reg_index = (first_dword >> 4) & 0xF;
|
||||
break;
|
||||
case DebugLogValueType::MemoryRelAddr:
|
||||
debug_log.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
|
||||
debug_log.rel_address =
|
||||
((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
|
||||
debug_log.rel_address = (static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
|
||||
break;
|
||||
case DebugLogValueType::MemoryOfsReg:
|
||||
debug_log.mem_type = static_cast<MemoryAccessType>((first_dword >> 4) & 0xF);
|
||||
debug_log.ofs_reg_index = (first_dword & 0xF);
|
||||
debug_log.ofs_reg_index = first_dword & 0xF;
|
||||
break;
|
||||
case DebugLogValueType::RegisterRelAddr:
|
||||
debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
|
||||
debug_log.rel_address =
|
||||
((static_cast<u64>(first_dword & 0xF) << 32ul) | static_cast<u64>(GetNextDword()));
|
||||
debug_log.addr_reg_index = (first_dword >> 4) & 0xF;
|
||||
debug_log.rel_address = (static_cast<u64>(first_dword & 0xF) << 32) | GetNextDword();
|
||||
break;
|
||||
case DebugLogValueType::RegisterOfsReg:
|
||||
debug_log.addr_reg_index = ((first_dword >> 4) & 0xF);
|
||||
debug_log.ofs_reg_index = (first_dword & 0xF);
|
||||
debug_log.addr_reg_index = (first_dword >> 4) & 0xF;
|
||||
debug_log.ofs_reg_index = first_dword & 0xF;
|
||||
break;
|
||||
}
|
||||
opcode.opcode = debug_log;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user