shader: Implement SR_Y_DIRECTION
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@ -72,6 +72,7 @@ Id EmitLocalInvocationId(EmitContext& ctx);
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Id EmitInvocationId(EmitContext& ctx);
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Id EmitSampleId(EmitContext& ctx);
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Id EmitIsHelperInvocation(EmitContext& ctx);
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Id EmitYDirection(EmitContext& ctx);
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Id EmitLoadLocal(EmitContext& ctx, Id word_offset);
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void EmitWriteLocal(EmitContext& ctx, Id word_offset, Id value);
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Id EmitUndefU1(EmitContext& ctx);
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@ -403,6 +403,13 @@ Id EmitIsHelperInvocation(EmitContext& ctx) {
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return ctx.OpLoad(ctx.U1, ctx.is_helper_invocation);
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}
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Id EmitYDirection(EmitContext& ctx) {
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if (ctx.profile.y_negate) {
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return ctx.Constant(ctx.F32[1], -1.0f);
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}
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return ctx.Constant(ctx.F32[1], 1.0f);
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}
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Id EmitLoadLocal(EmitContext& ctx, Id word_offset) {
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const Id pointer{ctx.OpAccessChain(ctx.private_u32, ctx.local_memory, word_offset)};
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return ctx.OpLoad(ctx.U32[1], pointer);
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@ -379,6 +379,10 @@ U1 IREmitter::IsHelperInvocation() {
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return Inst<U1>(Opcode::IsHelperInvocation);
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}
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F32 IREmitter::YDirection() {
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return Inst<F32>(Opcode::YDirection);
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}
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U32 IREmitter::LaneId() {
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return Inst<U32>(Opcode::LaneId);
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}
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@ -102,6 +102,7 @@ public:
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[[nodiscard]] U32 InvocationId();
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[[nodiscard]] U32 SampleId();
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[[nodiscard]] U1 IsHelperInvocation();
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[[nodiscard]] F32 YDirection();
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[[nodiscard]] U32 LaneId();
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@ -65,6 +65,7 @@ OPCODE(LocalInvocationId, U32x3,
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OPCODE(InvocationId, U32, )
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OPCODE(SampleId, U32, )
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OPCODE(IsHelperInvocation, U1, )
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OPCODE(YDirection, F32, )
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// Undefined
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OPCODE(UndefU1, U1, )
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@ -150,6 +150,8 @@ enum class SpecialRegister : u64 {
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return ir.SubgroupGtMask();
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case SpecialRegister::SR_GEMASK:
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return ir.SubgroupGeMask();
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case SpecialRegister::SR_Y_DIRECTION:
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return ir.BitCast<IR::U32>(ir.YDirection());
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default:
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throw NotImplementedException("S2R special register {}", special_register);
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}
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@ -97,6 +97,8 @@ struct Profile {
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std::optional<CompareFunction> alpha_test_func;
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float alpha_test_reference{};
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bool y_negate{};
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std::vector<TransformFeedbackVarying> xfb_varyings;
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};
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@ -82,6 +82,8 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
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alpha_test_ref = Common::BitCast<u32>(regs.alpha_test_ref);
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point_size = Common::BitCast<u32>(regs.point_size);
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y_negate.Assign(regs.screen_y_control.y_negate != 0 ? 1 : 0);
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if (maxwell3d.dirty.flags[Dirty::InstanceDivisors]) {
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maxwell3d.dirty.flags[Dirty::InstanceDivisors] = false;
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for (size_t index = 0; index < Maxwell::NumVertexArrays; ++index) {
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@ -202,6 +202,7 @@ struct FixedPipelineState {
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BitField<3, 1, u32> early_z;
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BitField<4, 1, u32> depth_enabled;
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BitField<5, 5, u32> depth_format;
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BitField<10, 1, u32> y_negate;
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};
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std::array<u8, Maxwell::NumRenderTargets> color_formats;
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@ -1116,6 +1116,7 @@ Shader::Profile PipelineCache::MakeProfile(const GraphicsPipelineCacheKey& key,
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break;
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}
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profile.force_early_z = key.state.early_z != 0;
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profile.y_negate = key.state.y_negate != 0;
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return profile;
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}
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