forked from Popn_Tools/popnhax
423 lines
14 KiB
C
423 lines
14 KiB
C
#include <stdlib.h>
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#include "ia32_implicit.h"
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#include "ia32_insn.h"
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#include "ia32_reg.h"
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#include "x86_operand_list.h"
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/* Conventions: Register operands which are aliases of another register
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* operand (e.g. AX in one operand and AL in another) assume that the
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* operands are different registers and that alias tracking will resolve
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* data flow. This means that something like
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* mov ax, al
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* would have 'write only' access for AX and 'read only' access for AL,
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* even though both AL and AX are read and written */
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typedef struct {
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uint32_t type;
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uint32_t operand;
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} op_implicit_list_t;
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static op_implicit_list_t list_aaa[] =
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/* 37 : AAA : rw AL */
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/* 3F : AAS : rw AL */
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{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}}; /* aaa */
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static op_implicit_list_t list_aad[] =
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/* D5 0A, D5 (ib) : AAD : rw AX */
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/* D4 0A, D4 (ib) : AAM : rw AX */
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{{ OP_R | OP_W, REG_WORD_OFFSET }, {0}}; /* aad */
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static op_implicit_list_t list_call[] =
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/* E8, FF, 9A, FF : CALL : rw ESP, rw EIP */
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/* C2, C3, CA, CB : RET : rw ESP, rw EIP */
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{{ OP_R | OP_W, REG_EIP_INDEX },
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{ OP_R | OP_W, REG_ESP_INDEX }, {0}}; /* call, ret */
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static op_implicit_list_t list_cbw[] =
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/* 98 : CBW : r AL, rw AX */
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{{ OP_R | OP_W, REG_WORD_OFFSET },
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{ OP_R, REG_BYTE_OFFSET}, {0}}; /* cbw */
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static op_implicit_list_t list_cwde[] =
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/* 98 : CWDE : r AX, rw EAX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET },
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{ OP_R, REG_WORD_OFFSET }, {0}}; /* cwde */
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static op_implicit_list_t list_clts[] =
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/* 0F 06 : CLTS : rw CR0 */
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{{ OP_R | OP_W, REG_CTRL_OFFSET}, {0}}; /* clts */
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static op_implicit_list_t list_cmpxchg[] =
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/* 0F B0 : CMPXCHG : rw AL */
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{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}}; /* cmpxchg */
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static op_implicit_list_t list_cmpxchgb[] =
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/* 0F B1 : CMPXCHG : rw EAX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}}; /* cmpxchg */
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static op_implicit_list_t list_cmpxchg8b[] =
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/* 0F C7 : CMPXCHG8B : rw EDX, rw EAX, r ECX, r EBX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET },
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{ OP_R | OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_R, REG_DWORD_OFFSET + 1 },
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{ OP_R, REG_DWORD_OFFSET + 3 }, {0}}; /* cmpxchg8b */
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static op_implicit_list_t list_cpuid[] =
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/* 0F A2 : CPUID : rw EAX, w EBX, w ECX, w EDX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET },
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{ OP_W, REG_DWORD_OFFSET + 1 },
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{ OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_W, REG_DWORD_OFFSET + 3 }, {0}}; /* cpuid */
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static op_implicit_list_t list_cwd[] =
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/* 99 : CWD/CWQ : rw EAX, w EDX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET },
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{ OP_W, REG_DWORD_OFFSET + 2 }, {0}}; /* cwd */
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static op_implicit_list_t list_daa[] =
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/* 27 : DAA : rw AL */
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/* 2F : DAS : rw AL */
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{{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}}; /* daa */
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static op_implicit_list_t list_idiv[] =
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/* F6 : DIV, IDIV : r AX, w AL, w AH */
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/* FIXED: first op was EAX, not Aw. TODO: verify! */
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{{ OP_R, REG_WORD_OFFSET },
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{ OP_W, REG_BYTE_OFFSET },
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{ OP_W, REG_BYTE_OFFSET + 4 }, {0}}; /* div */
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static op_implicit_list_t list_div[] =
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/* F7 : DIV, IDIV : rw EDX, rw EAX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}}; /* div */
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static op_implicit_list_t list_enter[] =
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/* C8 : ENTER : rw ESP w EBP */
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{{ OP_R | OP_W, REG_DWORD_OFFSET + 4 },
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{ OP_R, REG_DWORD_OFFSET + 5 }, {0}}; /* enter */
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static op_implicit_list_t list_f2xm1[] =
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/* D9 F0 : F2XM1 : rw ST(0) */
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/* D9 E1 : FABS : rw ST(0) */
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/* D9 E0 : FCHS : rw ST(0) */
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/* D9 FF : FCOS : rw ST(0)*/
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/* D8, DA : FDIV : rw ST(0) */
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/* D8, DA : FDIVR : rw ST(0) */
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/* D9 F2 : FPTAN : rw ST(0) */
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/* D9 FC : FRNDINT : rw ST(0) */
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/* D9 FB : FSINCOS : rw ST(0) */
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/* D9 FE : FSIN : rw ST(0) */
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/* D9 FA : FSQRT : rw ST(0) */
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/* D9 F4 : FXTRACT : rw ST(0) */
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{{ OP_R | OP_W, REG_FPU_OFFSET }, {0}}; /* f2xm1 */
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static op_implicit_list_t list_fcom[] =
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/* D8, DC, DE D9 : FCOM : r ST(0) */
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/* DE, DA : FICOM : r ST(0) */
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/* DF, D8 : FIST : r ST(0) */
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/* D9 E4 : FTST : r ST(0) */
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/* D9 E5 : FXAM : r ST(0) */
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{{ OP_R, REG_FPU_OFFSET }, {0}}; /* fcom */
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static op_implicit_list_t list_fpatan[] =
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/* D9 F3 : FPATAN : r ST(0), rw ST(1) */
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{{ OP_R, REG_FPU_OFFSET }, {0}}; /* fpatan */
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static op_implicit_list_t list_fprem[] =
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/* D9 F8, D9 F5 : FPREM : rw ST(0) r ST(1) */
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/* D9 FD : FSCALE : rw ST(0), r ST(1) */
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{{ OP_R | OP_W, REG_FPU_OFFSET },
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{ OP_R, REG_FPU_OFFSET + 1 }, {0}}; /* fprem */
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static op_implicit_list_t list_faddp[] =
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/* DE C1 : FADDP : r ST(0), rw ST(1) */
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/* DE E9 : FSUBP : r ST(0), rw ST(1) */
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/* D9 F1 : FYL2X : r ST(0), rw ST(1) */
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/* D9 F9 : FYL2XP1 : r ST(0), rw ST(1) */
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{{ OP_R, REG_FPU_OFFSET },
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{ OP_R | OP_W, REG_FPU_OFFSET + 1 }, {0}}; /* faddp */
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static op_implicit_list_t list_fucompp[] =
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/* DA E9 : FUCOMPP : r ST(0), r ST(1) */
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{{ OP_R, REG_FPU_OFFSET },
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{ OP_R, REG_FPU_OFFSET + 1 }, {0}}; /* fucompp */
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static op_implicit_list_t list_imul[] =
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/* F6 : IMUL : r AL, w AX */
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/* F6 : MUL : r AL, w AX */
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{{ OP_R, REG_BYTE_OFFSET },
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{ OP_W, REG_WORD_OFFSET }, {0}}; /* imul */
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static op_implicit_list_t list_mul[] =
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/* F7 : IMUL : rw EAX, w EDX */
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/* F7 : MUL : rw EAX, w EDX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET },
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{ OP_W, REG_DWORD_OFFSET + 2 }, {0}}; /* imul */
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static op_implicit_list_t list_lahf[] =
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/* 9F : LAHF : r EFLAGS, w AH */
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{{ OP_R, REG_FLAGS_INDEX },
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{ OP_W, REG_BYTE_OFFSET + 4 }, {0}}; /* lahf */
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static op_implicit_list_t list_ldmxcsr[] =
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/* 0F AE : LDMXCSR : w MXCSR SSE Control Status Reg */
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{{ OP_W, REG_MXCSG_INDEX }, {0}}; /* ldmxcsr */
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static op_implicit_list_t list_leave[] =
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/* C9 : LEAVE : rw ESP, w EBP */
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{{ OP_R | OP_W, REG_ESP_INDEX },
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{ OP_W, REG_DWORD_OFFSET + 5 }, {0}}; /* leave */
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static op_implicit_list_t list_lgdt[] =
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/* 0F 01 : LGDT : w GDTR */
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{{ OP_W, REG_GDTR_INDEX }, {0}}; /* lgdt */
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static op_implicit_list_t list_lidt[] =
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/* 0F 01 : LIDT : w IDTR */
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{{ OP_W, REG_IDTR_INDEX }, {0}}; /* lidt */
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static op_implicit_list_t list_lldt[] =
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/* 0F 00 : LLDT : w LDTR */
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{{ OP_W, REG_LDTR_INDEX }, {0}}; /* lldt */
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static op_implicit_list_t list_lmsw[] =
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/* 0F 01 : LMSW : w CR0 */
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{{ OP_W, REG_CTRL_OFFSET }, {0}}; /* lmsw */
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static op_implicit_list_t list_loop[] =
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/* E0, E1, E2 : LOOP : rw ECX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET + 1 }, {0}};/* loop */
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static op_implicit_list_t list_ltr[] =
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/* 0F 00 : LTR : w Task Register */
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{{ OP_W, REG_TR_INDEX }, {0}}; /* ltr */
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static op_implicit_list_t list_pop[] =
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/* 8F, 58, 1F, 07, 17, 0F A1, 0F A9 : POP : rw ESP */
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/* FF, 50, 6A, 68, 0E, 16, 1E, 06, 0F A0, 0F A8 : PUSH : rw ESP */
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{{ OP_R | OP_W, REG_ESP_INDEX }, {0}}; /* pop, push */
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static op_implicit_list_t list_popad[] =
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/* 61 : POPAD : rw esp, w edi esi ebp ebx edx ecx eax */
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{{ OP_R | OP_W, REG_ESP_INDEX },
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{ OP_W, REG_DWORD_OFFSET + 7 },
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{ OP_W, REG_DWORD_OFFSET + 6 },
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{ OP_W, REG_DWORD_OFFSET + 5 },
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{ OP_W, REG_DWORD_OFFSET + 3 },
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{ OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_W, REG_DWORD_OFFSET + 1 },
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{ OP_W, REG_DWORD_OFFSET }, {0}}; /* popad */
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static op_implicit_list_t list_popfd[] =
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/* 9D : POPFD : rw esp, w eflags */
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{{ OP_R | OP_W, REG_ESP_INDEX },
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{ OP_W, REG_FLAGS_INDEX }, {0}}; /* popfd */
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static op_implicit_list_t list_pushad[] =
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/* FF, 50, 6A, 68, 0E, 16, 1E, 06, 0F A0, 0F A8 : PUSH : rw ESP */
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/* 60 : PUSHAD : rw esp, r eax ecx edx ebx esp ebp esi edi */
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{{ OP_R | OP_W, REG_ESP_INDEX },
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{ OP_R, REG_DWORD_OFFSET },
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{ OP_R, REG_DWORD_OFFSET + 1 },
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{ OP_R, REG_DWORD_OFFSET + 2 },
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{ OP_R, REG_DWORD_OFFSET + 3 },
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{ OP_R, REG_DWORD_OFFSET + 5 },
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{ OP_R, REG_DWORD_OFFSET + 6 },
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{ OP_R, REG_DWORD_OFFSET + 7 }, {0}}; /* pushad */
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static op_implicit_list_t list_pushfd[] =
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/* 9C : PUSHFD : rw esp, r eflags */
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{{ OP_R | OP_W, REG_ESP_INDEX },
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{ OP_R, REG_FLAGS_INDEX }, {0}}; /* pushfd */
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static op_implicit_list_t list_rdmsr[] =
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/* 0F 32 : RDMSR : r ECX, w EDX, w EAX */
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{{ OP_R, REG_DWORD_OFFSET + 1 },
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{ OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_W, REG_DWORD_OFFSET }, {0}}; /* rdmsr */
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static op_implicit_list_t list_rdpmc[] =
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/* 0F 33 : RDPMC : r ECX, w EDX, w EAX */
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{{ OP_R, REG_DWORD_OFFSET + 1 },
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{ OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_W, REG_DWORD_OFFSET }, {0}}; /* rdpmc */
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static op_implicit_list_t list_rdtsc[] =
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/* 0F 31 : RDTSC : rw EDX, rw EAX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET + 2 },
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{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}}; /* rdtsc */
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static op_implicit_list_t list_rep[] =
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/* F3, F2 ... : REP : rw ECX */
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{{ OP_R | OP_W, REG_DWORD_OFFSET + 1 }, {0}};/* rep */
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static op_implicit_list_t list_rsm[] =
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/* 0F AA : RSM : r CR4, r CR0 */
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{{ OP_R, REG_CTRL_OFFSET + 4 },
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{ OP_R, REG_CTRL_OFFSET }, {0}}; /* rsm */
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static op_implicit_list_t list_sahf[] =
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/* 9E : SAHF : r ah, rw eflags (set SF ZF AF PF CF) */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sahf */
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static op_implicit_list_t list_sgdt[] =
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/* 0F : SGDT : r gdtr */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sgdt */
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static op_implicit_list_t list_sidt[] =
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/* 0F : SIDT : r idtr */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sidt */
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static op_implicit_list_t list_sldt[] =
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/* 0F : SLDT : r ldtr */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sldt */
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static op_implicit_list_t list_smsw[] =
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/* 0F : SMSW : r CR0 */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* smsw */
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static op_implicit_list_t list_stmxcsr[] =
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/* 0F AE : STMXCSR : r MXCSR */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* stmxcsr */
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static op_implicit_list_t list_str[] =
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/* 0F 00 : STR : r TR (task register) */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* str */
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static op_implicit_list_t list_sysenter[] =
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/* 0F 34 : SYSENTER : w cs, w eip, w ss, w esp, r CR0, w eflags
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* r sysenter_cs_msr, sysenter_esp_msr, sysenter_eip_msr */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sysenter */
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static op_implicit_list_t list_sysexit[] =
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/* 0F 35 : SYSEXIT : r edx, r ecx, w cs, w eip, w ss, w esp
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* r sysenter_cs_msr */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* sysexit */
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static op_implicit_list_t list_wrmsr[] =
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/* 0F 30 : WRMST : r edx, r eax, r ecx */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* wrmsr */
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static op_implicit_list_t list_xlat[] =
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/* D7 : XLAT : rw al r ebx (ptr) */
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/* TODO: finish this! */
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* xlat */
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/* TODO:
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* monitor 0f 01 c8 eax OP_R ecx OP_R edx OP_R
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* mwait 0f 01 c9 eax OP_R ecx OP_R
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*/
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static op_implicit_list_t list_monitor[] =
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* monitor */
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static op_implicit_list_t list_mwait[] =
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{{ OP_R, REG_DWORD_OFFSET }, {0}}; /* mwait */
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op_implicit_list_t *op_implicit_list[] = {
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/* This is a list of implicit operands which are read/written by
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* various x86 instructions. Note that modifications to the stack
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* register are mentioned here, but that additional information on
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* the effect an instruction has on the stack is contained in the
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* x86_insn_t 'stack_mod' and 'stack_mod_val' fields. Use of the
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* eflags register, i.e. setting, clearing, and testing flags, is
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* not recorded here but rather in the flags_set and flags_tested
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* fields of the x86_insn_t.*/
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NULL,
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list_aaa, list_aad, list_call, list_cbw, /* 1 - 4 */
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list_cwde, list_clts, list_cmpxchg, list_cmpxchgb, /* 5 - 8 */
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list_cmpxchg8b, list_cpuid, list_cwd, list_daa, /* 9 - 12 */
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list_idiv, list_div, list_enter, list_f2xm1, /* 13 - 16 */
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list_fcom, list_fpatan, list_fprem, list_faddp, /* 17 - 20 */
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list_fucompp, list_imul, list_mul, list_lahf, /* 21 - 24 */
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list_ldmxcsr, list_leave, list_lgdt, list_lidt, /* 25 - 28 */
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list_lldt, list_lmsw, list_loop, list_ltr, /* 29 - 32 */
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list_pop, list_popad, list_popfd, list_pushad, /* 33 - 36 */
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list_pushfd, list_rdmsr, list_rdpmc, list_rdtsc, /* 37 - 40 */
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/* NOTE: 'REP' is a hack since it is a prefix: if its position
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* in the table changes, then change IDX_IMPLICIT_REP in the .h */
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list_rep, list_rsm, list_sahf, list_sgdt, /* 41 - 44 */
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list_sidt, list_sldt, list_smsw, list_stmxcsr, /* 45 - 48 */
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list_str, list_sysenter, list_sysexit, list_wrmsr, /* 49 - 52 */
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list_xlat, list_monitor, list_mwait, /* 53 - 55*/
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NULL /* end of list */
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};
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#define LAST_IMPL_IDX 55
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static void handle_impl_reg( x86_op_t *op, uint32_t val ) {
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x86_reg_t *reg = &op->data.reg;
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op->type = op_register;
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ia32_handle_register( reg, (unsigned int) val );
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switch (reg->size) {
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case 1:
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op->datatype = op_byte; break;
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case 2:
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op->datatype = op_word; break;
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case 4:
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op->datatype = op_dword; break;
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case 8:
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op->datatype = op_qword; break;
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case 10:
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op->datatype = op_extreal; break;
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case 16:
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op->datatype = op_dqword; break;
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}
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return;
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}
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/* 'impl_idx' is the value from the opcode table: between 1 and LAST_IMPL_IDX */
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/* returns number of operands added */
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unsigned int ia32_insn_implicit_ops( x86_insn_t *insn, unsigned int impl_idx ) {
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op_implicit_list_t *list;
|
|
x86_op_t *op;
|
|
unsigned int num = 0;
|
|
|
|
if (! impl_idx || impl_idx > LAST_IMPL_IDX ) {
|
|
return 0;
|
|
}
|
|
|
|
for ( list = op_implicit_list[impl_idx]; list->type; list++, num++ ) {
|
|
enum x86_op_access access = (enum x86_op_access) OP_PERM(list->type);
|
|
enum x86_op_flags flags = (enum x86_op_flags) (OP_FLAGS(list->type) >> 12);
|
|
|
|
op = NULL;
|
|
/* In some cases (MUL), EAX is an implicit operand hardcoded in
|
|
* the instruction without being explicitly listed in assembly.
|
|
* For this situation, find the hardcoded operand and add the
|
|
* implied flag rather than adding a new implicit operand. */
|
|
x86_oplist_t * existing;
|
|
if (ia32_true_register_id(list->operand) == REG_DWORD_OFFSET) {
|
|
for ( existing = insn->operands; existing; existing = existing->next ) {
|
|
if (existing->op.type == op_register &&
|
|
existing->op.data.reg.id == list->operand) {
|
|
op = &existing->op;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
if (!op) {
|
|
op = x86_operand_new( insn );
|
|
/* all implicit operands are registers */
|
|
handle_impl_reg( op, list->operand );
|
|
/* decrement the 'explicit count' incremented by default in
|
|
* x86_operand_new */
|
|
insn->explicit_count = insn->explicit_count -1;
|
|
}
|
|
if (!op) {
|
|
return num; /* gah! return early */
|
|
}
|
|
op->access |= access;
|
|
op->flags |= flags;
|
|
op->flags |= op_implied;
|
|
}
|
|
|
|
return num;
|
|
}
|