mirror of
https://github.com/CrazyRedMachine/popnhax.git
synced 2024-11-27 23:40:50 +01:00
235 lines
7.5 KiB
C
235 lines
7.5 KiB
C
#include <stdlib.h>
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#include <string.h>
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#include "ia32_reg.h"
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#include "ia32_insn.h"
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#define NUM_X86_REGS 92
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/* register sizes */
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#define REG_DWORD_SIZE 4
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#define REG_WORD_SIZE 2
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#define REG_BYTE_SIZE 1
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#define REG_MMX_SIZE 8
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#define REG_SIMD_SIZE 16
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#define REG_DEBUG_SIZE 4
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#define REG_CTRL_SIZE 4
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#define REG_TEST_SIZE 4
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#define REG_SEG_SIZE 2
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#define REG_FPU_SIZE 10
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#define REG_FLAGS_SIZE 4
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#define REG_FPCTRL_SIZE 2
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#define REG_FPSTATUS_SIZE 2
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#define REG_FPTAG_SIZE 2
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#define REG_EIP_SIZE 4
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#define REG_IP_SIZE 2
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/* REGISTER ALIAS TABLE:
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*
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* NOTE: the MMX register mapping is fixed to the physical registers
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* used by the FPU. The floating FP stack does not effect the location
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* of the MMX registers, so this aliasing is not 100% accurate.
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* */
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static struct {
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unsigned char alias; /* id of register this is an alias for */
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unsigned char shift; /* # of bits register must be shifted */
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} ia32_reg_aliases[] = {
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{ 0,0 },
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{ REG_DWORD_OFFSET, 0 }, /* al : 1 */
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{ REG_DWORD_OFFSET, 8 }, /* ah : 2 */
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{ REG_DWORD_OFFSET, 0 }, /* ax : 3 */
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{ REG_DWORD_OFFSET + 1, 0 }, /* cl : 4 */
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{ REG_DWORD_OFFSET + 1, 8 }, /* ch : 5 */
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{ REG_DWORD_OFFSET + 1, 0 }, /* cx : 6 */
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{ REG_DWORD_OFFSET + 2, 0 }, /* dl : 7 */
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{ REG_DWORD_OFFSET + 2, 8 }, /* dh : 8 */
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{ REG_DWORD_OFFSET + 2, 0 }, /* dx : 9 */
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{ REG_DWORD_OFFSET + 3, 0 }, /* bl : 10 */
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{ REG_DWORD_OFFSET + 3, 8 }, /* bh : 11 */
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{ REG_DWORD_OFFSET + 3, 0 }, /* bx : 12 */
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{ REG_DWORD_OFFSET + 4, 0 }, /* sp : 13 */
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{ REG_DWORD_OFFSET + 5, 0 }, /* bp : 14 */
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{ REG_DWORD_OFFSET + 6, 0 }, /* si : 15 */
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{ REG_DWORD_OFFSET + 7, 0 }, /* di : 16 */
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{ REG_EIP_INDEX, 0 }, /* ip : 17 */
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{ REG_FPU_OFFSET, 0 }, /* mm0 : 18 */
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{ REG_FPU_OFFSET + 1, 0 }, /* mm1 : 19 */
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{ REG_FPU_OFFSET + 2, 0 }, /* mm2 : 20 */
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{ REG_FPU_OFFSET + 3, 0 }, /* mm3 : 21 */
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{ REG_FPU_OFFSET + 4, 0 }, /* mm4 : 22 */
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{ REG_FPU_OFFSET + 5, 0 }, /* mm5 : 23 */
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{ REG_FPU_OFFSET + 6, 0 }, /* mm6 : 24 */
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{ REG_FPU_OFFSET + 7, 0 } /* mm7 : 25 */
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};
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/* REGISTER TABLE: size, type, and name of every register in the
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* CPU. Does not include MSRs since the are, after all,
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* model specific. */
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static struct {
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unsigned int size;
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enum x86_reg_type type;
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unsigned int alias;
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char mnemonic[8];
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} ia32_reg_table[NUM_X86_REGS + 2] = {
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{ 0, 0, 0, "" },
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/* REG_DWORD_OFFSET */
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{ REG_DWORD_SIZE, reg_gen | reg_ret, 0, "eax" },
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{ REG_DWORD_SIZE, reg_gen | reg_count, 0, "ecx" },
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{ REG_DWORD_SIZE, reg_gen, 0, "edx" },
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{ REG_DWORD_SIZE, reg_gen, 0, "ebx" },
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/* REG_ESP_INDEX */
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{ REG_DWORD_SIZE, reg_gen | reg_sp, 0, "esp" },
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{ REG_DWORD_SIZE, reg_gen | reg_fp, 0, "ebp" },
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{ REG_DWORD_SIZE, reg_gen | reg_src, 0, "esi" },
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{ REG_DWORD_SIZE, reg_gen | reg_dest, 0, "edi" },
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/* REG_WORD_OFFSET */
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{ REG_WORD_SIZE, reg_gen | reg_ret, 3, "ax" },
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{ REG_WORD_SIZE, reg_gen | reg_count, 6, "cx" },
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{ REG_WORD_SIZE, reg_gen, 9, "dx" },
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{ REG_WORD_SIZE, reg_gen, 12, "bx" },
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{ REG_WORD_SIZE, reg_gen | reg_sp, 13, "sp" },
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{ REG_WORD_SIZE, reg_gen | reg_fp, 14, "bp" },
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{ REG_WORD_SIZE, reg_gen | reg_src, 15, "si" },
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{ REG_WORD_SIZE, reg_gen | reg_dest, 16, "di" },
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/* REG_BYTE_OFFSET */
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{ REG_BYTE_SIZE, reg_gen, 1, "al" },
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{ REG_BYTE_SIZE, reg_gen, 4, "cl" },
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{ REG_BYTE_SIZE, reg_gen, 7, "dl" },
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{ REG_BYTE_SIZE, reg_gen, 10, "bl" },
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{ REG_BYTE_SIZE, reg_gen, 2, "ah" },
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{ REG_BYTE_SIZE, reg_gen, 5, "ch" },
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{ REG_BYTE_SIZE, reg_gen, 8, "dh" },
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{ REG_BYTE_SIZE, reg_gen, 11, "bh" },
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/* REG_MMX_OFFSET */
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{ REG_MMX_SIZE, reg_simd, 18, "mm0" },
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{ REG_MMX_SIZE, reg_simd, 19, "mm1" },
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{ REG_MMX_SIZE, reg_simd, 20, "mm2" },
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{ REG_MMX_SIZE, reg_simd, 21, "mm3" },
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{ REG_MMX_SIZE, reg_simd, 22, "mm4" },
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{ REG_MMX_SIZE, reg_simd, 23, "mm5" },
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{ REG_MMX_SIZE, reg_simd, 24, "mm6" },
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{ REG_MMX_SIZE, reg_simd, 25, "mm7" },
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/* REG_SIMD_OFFSET */
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm0" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm1" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm2" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm3" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm4" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm5" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm6" },
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{ REG_SIMD_SIZE, reg_simd, 0, "xmm7" },
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/* REG_DEBUG_OFFSET */
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr0" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr1" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr2" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr3" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr4" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr5" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr6" },
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{ REG_DEBUG_SIZE, reg_sys, 0, "dr7" },
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/* REG_CTRL_OFFSET */
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{ REG_CTRL_SIZE, reg_sys, 0, "cr0" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr1" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr2" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr3" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr4" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr5" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr6" },
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{ REG_CTRL_SIZE, reg_sys, 0, "cr7" },
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/* REG_TEST_OFFSET */
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{ REG_TEST_SIZE, reg_sys, 0, "tr0" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr1" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr2" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr3" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr4" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr5" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr6" },
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{ REG_TEST_SIZE, reg_sys, 0, "tr7" },
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/* REG_SEG_OFFSET */
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{ REG_SEG_SIZE, reg_seg, 0, "es" },
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{ REG_SEG_SIZE, reg_seg, 0, "cs" },
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{ REG_SEG_SIZE, reg_seg, 0, "ss" },
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{ REG_SEG_SIZE, reg_seg, 0, "ds" },
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{ REG_SEG_SIZE, reg_seg, 0, "fs" },
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{ REG_SEG_SIZE, reg_seg, 0, "gs" },
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/* REG_LDTR_INDEX */
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{ REG_DWORD_SIZE, reg_sys, 0, "ldtr" },
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/* REG_GDTR_INDEX */
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{ REG_DWORD_SIZE, reg_sys, 0, "gdtr" },
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/* REG_FPU_OFFSET */
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{ REG_FPU_SIZE, reg_fpu, 0, "st(0)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(1)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(2)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(3)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(4)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(5)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(6)" },
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{ REG_FPU_SIZE, reg_fpu, 0, "st(7)" },
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/* REG_FLAGS_INDEX : 81 */
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{ REG_FLAGS_SIZE, reg_cond, 0, "eflags" },
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/* REG_FPCTRL_INDEX : 82*/
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{ REG_FPCTRL_SIZE, reg_fpu | reg_sys, 0, "fpctrl" },
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/* REG_FPSTATUS_INDEX : 83*/
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{ REG_FPSTATUS_SIZE, reg_fpu | reg_sys, 0, "fpstat" },
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/* REG_FPTAG_INDEX : 84 */
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{ REG_FPTAG_SIZE, reg_fpu | reg_sys, 0, "fptag" },
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/* REG_EIP_INDEX : 85 */
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{ REG_EIP_SIZE, reg_pc, 0, "eip" },
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/* REG_IP_INDEX : 86 */
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{ REG_IP_SIZE, reg_pc, 17, "ip" },
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/* REG_IDTR_INDEX : 87 */
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{ REG_DWORD_SIZE, reg_sys, 0, "idtr" },
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/* REG_MXCSG_INDEX : SSE Control Reg : 88 */
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{ REG_DWORD_SIZE, reg_sys | reg_simd, 0, "mxcsr" },
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/* REG_TR_INDEX : Task Register : 89 */
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{ 16 + 64, reg_sys, 0, "tr" },
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/* REG_CSMSR_INDEX : SYSENTER_CS_MSR : 90 */
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{ REG_DWORD_SIZE, reg_sys, 0, "cs_msr" },
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/* REG_ESPMSR_INDEX : SYSENTER_ESP_MSR : 91 */
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{ REG_DWORD_SIZE, reg_sys, 0, "esp_msr" },
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/* REG_EIPMSR_INDEX : SYSENTER_EIP_MSR : 92 */
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{ REG_DWORD_SIZE, reg_sys, 0, "eip_msr" },
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{ 0 }
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};
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static size_t sz_regtable = NUM_X86_REGS + 1;
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void ia32_handle_register( x86_reg_t *reg, size_t id ) {
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unsigned int alias;
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if (! id || id > sz_regtable ) {
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return;
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}
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memset( reg, 0, sizeof(x86_reg_t) );
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strncpy( reg->name, ia32_reg_table[id].mnemonic, MAX_REGNAME );
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reg->type = ia32_reg_table[id].type;
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reg->size = ia32_reg_table[id].size;
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alias = ia32_reg_table[id].alias;
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if ( alias ) {
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reg->alias = ia32_reg_aliases[alias].alias;
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reg->shift = ia32_reg_aliases[alias].shift;
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}
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reg->id = id;
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return;
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}
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size_t ia32_true_register_id( size_t id ) {
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size_t reg;
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if (! id || id > sz_regtable ) {
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return 0;
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}
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reg = id;
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if (ia32_reg_table[reg].alias) {
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reg = ia32_reg_aliases[ia32_reg_table[reg].alias].alias;
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}
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return reg;
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}
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