{% extends "sega.html" %} {% macro nameTable(name, guid=None) %}
Device Name | {% if name %}\Device\{{ name }} {% endif %} |
Linked To | {% if name %}\DosDevices\{{name}} (\\.\{{name}} ){% endif %} |
Device GUID | {% if guid %}{{ guid }} {% endif %} |
Ring* systems makes use of a number of (mostly) bespoke drivers, listed below:
columba.sys
mxcmos.sys
mxhwreset.sys
mxjvs.sys
mxparallel.sys
mxsmbus.sys
mxsram.sys
mxsram_pci_isa_bridge.sys
mxsram_pcmcia.sys
mxsuperio.sys
mxusbdevice.sys
Columba is a driver used to fetch DMI information about the current system.
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c406104 |
{{ ioctl("0x9c406104") }} |
Read the DMI at a given offset |
mxcmos is unknown currently
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c402000 |
{{ ioctl("0x9c402000") }} |
0xcf9
mxjvs is the driver used to communicate with the JVS IO board connected to the Ring* PC via the JVS USB port.
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c402000 |
{{ ioctl("0x9c402000") }} |
variable | variable | Exchange JVS packets with the JVS IO board |
\Device\Serial3
86e0d1e0-8089-11d0-9ce4-08003e301f73
mxparallel is a wrapper driver for the parallel port used to communicate with the keychip
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c40a000 |
{{ ioctl("0x9c40a000") }} |
Write data | ||
0x9c406004 |
{{ ioctl("0x9c406004") }} |
Read data | ||
0x9c40a008 |
{{ ioctl("0x9c40a008") }} |
Write status | ||
0x9c40600c |
{{ ioctl("0x9c40600c") }} |
Read status | ||
0x9c40a010 |
{{ ioctl("0x9c40a010") }} |
Write control | ||
0x9c406014 |
{{ ioctl("0x9c406014") }} |
Read control | ||
0x9c40a018 |
{{ ioctl("0x9c40a018") }} |
Write flags | ||
0x9c40601c |
{{ ioctl("0x9c40601c") }} |
Read flags |
\Device\ParallelPort0
This driver communicates with the system message bus chip on the motherboard. This driver appears to be a slightly modified reference driver from Intel. The exact chipset used varies depending on the system:
RingWide | Intel(R) 82801G(ICH7 Family)SMBus Controller |
RingEdge | Intel(R) ICH9 SMBus Controller |
RingEdge 2 | Intel(R) 5 Series/3400 Series Chipset Family SMBus Controller |
Devices currently confirmed to be located on the system message bus:
Address | Device |
0x20 |
PCA9535; used for DIP switches |
0x30 |
|
0x55 |
|
0x57 |
EEPROM |
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c406000 |
{{ ioctl("0x9c406000") }} |
0 | 4 | Not totally understood, but appears to retrieve the port number |
0x9c402004 |
{{ ioctl("0x9c402004") }} |
25h | 25h | Exchange data over the smbus |
0x9c406008 |
{{ ioctl("0x9c406008") }} |
0 | 4 | Retrieve the driver version |
0x9c40200c |
{{ ioctl("0x9c40200c") }} |
27h | 27h | Exchange data with an I2C device over the smbus |
Unsure
The on-board SRAM. This device driver also supports reading and writing like a file.
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x70000 |
IOCTL_DISK_GET_DRIVE_GEOMETRY |
0 | 18h | |
0x7405c |
IOCTL_DISK_GET_LENGTH_INFO |
0 | 8 | |
0x9c406000 |
{{ ioctl("0x9c406000") }} |
Ping | ||
0x9c406004 |
{{ ioctl("0x9c406004") }} |
Get sector size | ||
0x9c406008 |
{{ ioctl("0x9c406008") }} |
Get version |
\Device\memcard0
mxsram_pci_isa_bridge is unknown currently
mxsram_pcmcia is unknown currently
This driver communicates with some additional on-board devices. Notably EEPROM and the W83791D hardware monitor.
IOCTL Code | #define | Bytes in | Bytes out | Meaning |
0x9c406000 |
{{ ioctl("0x9c406000") }} |
Ping | ||
0x9c402004 |
{{ ioctl("0x9c402004") }} |
Read | ||
0x9c40a008 |
{{ ioctl("0x9c40a008") }} |
Write | ||
0x9c40200c |
{{ ioctl("0x9c40200c") }} |
Hardware monitor Read | ||
0x9c40a010 |
{{ ioctl("0x9c40a010") }} |
Hardware monitor write |
mxsram_pcmcia is unknown currently
{% endblock %}