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101 lines
2.7 KiB
Plaintext
101 lines
2.7 KiB
Plaintext
# 573in1 - Copyright (C) 2022-2024 spicyjpeg
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#
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# 573in1 is free software: you can redistribute it and/or modify it under the
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# terms of the GNU General Public License as published by the Free Software
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# Foundation, either version 3 of the License, or (at your option) any later
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# version.
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#
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# 573in1 is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# 573in1. If not, see <https://www.gnu.org/licenses/>.
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# This script is roughly similar to the built-in synth_xilinx command, with the
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# appropriate modifications made in order to output gate netlists rather than
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# precompiled LUTs (which are not supported by the ISE mapper for Spartan-XL
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# devices).
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## Input and preliminary optimization
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read_verilog src/primitives/carry.v
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read_verilog src/primitives/io.v
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read_verilog src/primitives/logic.v
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read_verilog src/primitives/memory.v
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read_verilog src/spartanxl/alu.v
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read_verilog src/spartanxl/compare.v
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read_verilog src/spartanxl/counter.v
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read_verilog src/spartanxl/mux.v
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read_verilog src/spartanxl/register.v
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read_verilog src/main/dram.v
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read_verilog src/main/main.v
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read_verilog src/main/mp3.v
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read_verilog src/main/uart.v
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read_verilog src/main/util.v
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hierarchy -check -top FPGA
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proc
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flatten -noscopeinfo
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tribuf
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deminout
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opt_expr
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opt_clean
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#check
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opt -nodffe -nosdff
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fsm
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opt
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wreduce
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peepopt
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opt_clean
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## Conversion to gate-level representation
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techmap -D LUT_WIDTH=4 -map +/cmp2lut.v -map +/cmp2lcu.v
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alumacc
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share
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opt
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memory -nomap
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opt_clean
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memory_libmap -lib yosys/lutram.txt
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opt -fast -full
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memory_map
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opt -full
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techmap -map +/techmap.v
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opt -fast
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clean
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## FPGA-specific mapping
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dfflegalize -cell $_DFFE_PP?P_ r -cell $_DLATCH_PP?_ r
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opt_expr -mux_undef -noclkinv
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abc -liberty yosys/logic.lib
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#hilomap -hicell VCC P -locell GND G
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#clkbufmap -buf BUFGLS O:I
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iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad _OBUFE E:I:O -tinoutpad _IOBUFE E:O:I:IO -ignore BUFGLS I -ignore IFDX D -ignore IFDXI D -ignore OFDX Q -ignore OFDXI Q -ignore OFDTX O -ignore OFDTXI O
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techmap -map yosys/cellmap.v
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clean
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## Output
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# HACK: Yosys complains or inserts extraneous cells if these attributes, which
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# have already been processed, are not stripped out manually.
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setattr -unset init
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setattr -unset wand
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setattr -unset wor
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hierarchy -check
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autoname
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stat
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#check -mapped -noinit
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blackbox =A:whitebox
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write_verilog -norename build/synth.v
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iopadmap -bits -inpad IPAD IPAD -outpad OPAD OPAD -inoutpad IOPAD IOPAD -ignore IPAD IPAD -ignore OPAD OPAD -ignore IOPAD IOPAD
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write_edif -attrprop -top FPGA -pvector bra -lsbidx build/synth.edf
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