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156 lines
6.0 KiB
Markdown
156 lines
6.0 KiB
Markdown
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# Digital I/O board FPGA bitstream
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## Overview
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The System 573's digital I/O board has the bulk of its logic split across two
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different chips:
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- an XCS40XL Spartan-XL FPGA, implementing pretty much all of the board's
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functionality and driving most of the light outputs;
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- an XC9536 CPLD, responsible for driving the remaining outputs and bringing up
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the FPGA.
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While the CPLD is factory-programmed and its registers can be accessed without
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any prior initialization, the FPGA must be configured by uploading a bitstream
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prior to accessing anything connected to it. This includes the DS2401 that holds
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the board's identifier, so a bitstream is required by the tool even though it
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does not otherwise make use of the MP3 decoder, additional RAM or any other
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hardware on the board.
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The `fpga` directory contains the source code for a simple bitstream that
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implements a small subset of the functionality provided by Konami's bitstreams,
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allowing the tool to control light outputs and read the DS2401 without having to
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redistribute any files extracted from games. See below for instructions on
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building it.
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For more information about the board's hardware and wiring, see:
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- [Digital I/O board](https://psx-spx.consoledev.net/konamisystem573/#digital-io-board-gx894-pwbba)
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- [XCS40XL FPGA pin mapping](https://psx-spx.consoledev.net/konamisystem573/#xcs40xl-fpga-pin-mapping)
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## Register map
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### `0x1f640080`: Magic number
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| Bits | RW | Description |
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| ---: | :- | :---------------------- |
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| 0-15 | R | Magic number (`0x573f`) |
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Note that the number is different from the one used by Konami (`0x1234`).
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### `0x1f6400e0`: Light output bank A
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| Bits | RW | Description |
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| ---: | :- | :----------------------------------- |
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| 0-11 | | _Unused_ |
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| 12 | W | Output A4 (0 = grounded, 1 = high-z) |
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| 13 | W | Output A5 (0 = grounded, 1 = high-z) |
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| 14 | W | Output A6 (0 = grounded, 1 = high-z) |
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| 15 | W | Output A7 (0 = grounded, 1 = high-z) |
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### `0x1f6400e2`: Light output bank A
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| Bits | RW | Description |
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| ---: | :- | :----------------------------------- |
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| 0-11 | | _Unused_ |
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| 12 | W | Output A0 (0 = grounded, 1 = high-z) |
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| 13 | W | Output A1 (0 = grounded, 1 = high-z) |
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| 14 | W | Output A2 (0 = grounded, 1 = high-z) |
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| 15 | W | Output A3 (0 = grounded, 1 = high-z) |
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### `0x1f6400e4`: Light output bank B
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| Bits | RW | Description |
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| ---: | :- | :----------------------------------- |
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| 0-11 | | _Unused_ |
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| 12 | W | Output B4 (0 = grounded, 1 = high-z) |
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| 13 | W | Output B5 (0 = grounded, 1 = high-z) |
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| 14 | W | Output B6 (0 = grounded, 1 = high-z) |
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| 15 | W | Output B7 (0 = grounded, 1 = high-z) |
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### `0x1f6400e6`: Light output bank D
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| Bits | RW | Description |
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| ---: | :- | :----------------------------------- |
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| 0-11 | | _Unused_ |
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| 12 | W | Output D0 (0 = grounded, 1 = high-z) |
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| 13 | W | Output D1 (0 = grounded, 1 = high-z) |
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| 14 | W | Output D2 (0 = grounded, 1 = high-z) |
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| 15 | W | Output D3 (0 = grounded, 1 = high-z) |
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### `0x1f6400ee` (FPGA, DDR/Mambo bitstream): **1-wire bus**
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When read:
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| Bits | RW | Description |
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| ----: | :- | :------------------------ |
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| 0-11 | | _Unused_ |
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| 12 | R | DS2401 1-wire bus readout |
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| 13 | R | DS2433 1-wire bus readout |
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| 14-15 | | _Unused_ |
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When written:
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| Bits | RW | Description |
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| ----: | :- | :----------------------------------------------------------- |
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| 0-11 | | _Unused_ |
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| 12 | W | Drive DS2401 1-wire bus low (1 = pull to ground, 0 = high-z) |
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| 13 | W | Drive DS2433 1-wire bus low (1 = pull to ground, 0 = high-z) |
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| 14-15 | | _Unused_ |
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Bit 13 is mapped to the bus of the (normally unpopulated) DS2433 footprint. It
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is currently unclear whether and how Konami's bitstreams expose this bus.
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## Building the bitstream
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**NOTE**: building the bitstream is *not* required in order to compile the
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project as a prebuilt copy is provided in the `data` directory. This section is
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only relevant if you wish to modify the source files in the `fpga/src`
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directory, for instance to add new functionality.
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You will have to obtain and install a copy of Xilinx ISE 4.2 (the last release
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to support Spartan-XL devices). The toolchain is Windows only but seems to work
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under Wine; the installer does not, however it is possible to sidestep it by
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manually invoking the Java-based extractor included in the installer as follows:
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```bash
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# Replace /opt/xilinx with a suitable target location and run from the
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# installation package's root
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find car -iname '*.car' -exec \
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java -cp ce/CarExpand.jar:ce/marimba.zip:ce/tuner.zip \
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com.xilinx.carexp.CarExp '{}' /opt/xilinx \;
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```
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Due to ISE's limitations, the full absolute path to the target directory
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(`C:\Xilinx` by default) must be less than 64 characters long and cannot contain
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any spaces. You will additionally need a recent version of
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[Yosys](https://github.com/YosysHQ/yosys), which can be installed as part of
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the [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build#installation)
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and should be added to the `PATH` environment variable.
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Once both are installed, you may synthesize the bitstream by running the
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following commands from the project's `fpga` directory (replace the ISE path
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appropriately):
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```bash
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# Windows
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set XILINX=C:\Xilinx
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mkdir build
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yosys fpga.ys
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.\runISE.bat
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# Linux (using Wine)
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export XILINX=/opt/xilinx
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mkdir -p build
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yosys fpga.ys
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wine runISE.bat
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```
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The bitstream can then be visually inspected using the ISE FPGA editor:
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```bash
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"%XILINX%\bin\nt\fpga_editor.exe" build\fpga.ncd # Windows
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wine "$XILINX/bit/nt/fpga_editor.exe" build/fpga.ncd # Linux (using Wine)
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```
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