Upgrade Schematics to Kicad 7.0

This commit is contained in:
Chrissy 2023-04-04 11:16:39 +01:00
parent e6ed4cc07b
commit 478080df83
17 changed files with 101536 additions and 11902 deletions

View File

@ -34,9 +34,9 @@
"other_text_thickness": 0.15,
"other_text_upright": false,
"pads": {
"drill": 1.0,
"height": 1.8,
"width": 1.8
"drill": 1.2,
"height": 2.889996,
"width": 1.875396
},
"silk_line_width": 0.15,
"silk_text_italic": false,
@ -55,7 +55,10 @@
"width": 0.0
}
],
"drc_exclusions": [],
"drc_exclusions": [
"solder_mask_bridge|84280000|39080000|ead42c56-2733-4ba6-a97d-fdb019c895b3|b4360e04-00b0-4f70-8aaa-1a95707bdbf2",
"solder_mask_bridge|86820000|36540000|ead42c56-2733-4ba6-a97d-fdb019c895b3|9391bc00-d29d-4e08-833e-7d25ce1c5043"
],
"meta": {
"version": 2
},
@ -65,7 +68,7 @@
"connection_width": "warning",
"copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error",
"courtyards_overlap": "ignore",
"diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error",
@ -111,11 +114,11 @@
},
"rules": {
"max_error": 0.005,
"min_clearance": 0.13,
"min_clearance": 0.08,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.0,
"min_hole_clearance": 0.75,
"min_hole_to_hole": 0.25,
"min_hole_clearance": 0.127,
"min_hole_to_hole": 0.19999999999999998,
"min_microvia_diameter": 0.19999999999999998,
"min_microvia_drill": 0.09999999999999999,
"min_resolved_spokes": 1,
@ -123,7 +126,7 @@
"min_text_height": 0.7999999999999999,
"min_text_thickness": 0.12,
"min_through_hole_diameter": 0.3,
"min_track_width": 0.16,
"min_track_width": 0.127,
"min_via_annular_width": 0.049999999999999996,
"min_via_diameter": 0.39999999999999997,
"solder_mask_clearance": 0.0,
@ -374,13 +377,14 @@
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"endpoint_off_grid": "ignore",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
@ -396,7 +400,7 @@
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"pin_to_pin": "error",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"simulation_model_issue": "error",
@ -418,8 +422,8 @@
"classes": [
{
"bus_width": 12,
"clearance": 0.16,
"diff_pair_gap": 0.25,
"clearance": 0.08,
"diff_pair_gap": 0.127,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
@ -428,7 +432,7 @@
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.16,
"track_width": 0.127,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6
@ -488,7 +492,9 @@
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65,

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@ -147,4 +147,110 @@
(pad "b48" thru_hole circle (at 56.73 -6.48) (size 1.524 1.524) (drill 0.9) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp d918eeb5-0b91-4d99-915a-8df6cc60c4c9))
(pad "b49" thru_hole circle (at 59.27 -6.48) (size 1.524 1.524) (drill 0.9) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp facdbc7d-baee-43c9-b747-f30fda36975e))
(pad "b50" thru_hole circle (at 61.81 -6.48) (size 1.524 1.524) (drill 0.9) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp 7c77d1df-6f59-4b7f-a3ce-93b448fb04ab))
(zone (net 0) (net_name "") (layer "F.Cu") (tstamp 7f577561-98d1-408f-a00a-8411870b4c45) (hatch edge 0.508)
(connect_pads (clearance 0))
(min_thickness 0.254) (filled_areas_thickness no)
(keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508) (island_removal_mode 2) (island_area_min 10))
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)
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(zone (net 0) (net_name "") (layer "F.Cu") (tstamp 1f46787f-a537-49b0-a5d4-a517582699e0) (hatch edge 0.508)
(connect_pads (clearance 0))
(min_thickness 0.254) (filled_areas_thickness no)
(keepout (tracks allowed) (vias allowed) (pads allowed) (copperpour not_allowed) (footprints allowed))
(fill (thermal_gap 0.508) (thermal_bridge_width 0.508) (island_removal_mode 2) (island_area_min 10))
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@ -29,10 +29,8 @@
(stroke (width 0.3) (type default)) (layer "F.SilkS") (tstamp 5dcc8914-19d2-4345-8294-1e98a1dd95f4))
(fp_line (start 12.17 11.88) (end 12.17 3.92)
(stroke (width 0.3) (type default)) (layer "F.SilkS") (tstamp 3f334b78-552d-4a76-a0a6-c2e08e92ceab))
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(pad "" thru_hole rect (at -8.24 8.17) (size 1.875396 2.889996) (drill oval 1.2 2.3) (layers *.Mask "F.Cu" "In1.Cu" "B.Cu") (tstamp a6ee399e-c428-47d8-acde-7f83ea52d4b2))
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