Cool_Tools/NeoGeoAES-3.5
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NeoGeo AES 3.5 Schematics and PCB
101 Commits 1 Branch 0 Tags 281 MiB
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Chrissy a5c002ab46 Changed Power input on DC Jack to be +9v instead of VCC 
Zero errors on PCB
2023-04-04 16:35:23 +01:00
_autosave-NeoGeoAES3_5-backups Ongoing PCB updates 2022-12-13 16:59:09 +00:00
images Ongoing PCB updates 2022-12-13 16:59:09 +00:00
libs Upgrade Schematics to Kicad 7.0 2023-04-04 11:16:39 +01:00
sheets Changed Power input on DC Jack to be +9v instead of VCC 2023-04-04 16:35:23 +01:00
.gitignore update ignored files 2022-12-03 22:08:06 +00:00
fp-info-cache Changed Power input on DC Jack to be +9v instead of VCC 2023-04-04 16:35:23 +01:00
fp-lib-table Initial Commit of Schematics 2022-12-03 20:24:55 +00:00
LICENSE Initial commit 2022-12-03 20:21:02 +00:00
NeoGeoAES3_5.kicad_pcb Changed Power input on DC Jack to be +9v instead of VCC 2023-04-04 16:35:23 +01:00
NeoGeoAES3_5.kicad_prl Changed Power input on DC Jack to be +9v instead of VCC 2023-04-04 16:35:23 +01:00
NeoGeoAES3_5.kicad_pro More VCC/GND Plane PCB Updates 2023-04-04 16:06:18 +01:00
NeoGeoAES3_5.kicad_sch Upgrade Schematics to Kicad 7.0 2023-04-04 11:16:39 +01:00
README.md Initial commit 2022-12-03 20:21:02 +00:00
sym-lib-table Changed Power input on DC Jack to be +9v instead of VCC 2023-04-04 16:35:23 +01:00

README.md

NeoGeoAES-3.5

NeoGeo AES 3.5 Schematics and PCB