Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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using ARMeilleure;
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2019-06-01 02:31:10 +02:00
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using LibHac.Fs;
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2019-02-11 13:00:32 +01:00
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using OpenTK.Input;
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using Ryujinx.Common;
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using Ryujinx.Common.Logging;
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using Ryujinx.HLE;
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using Ryujinx.HLE.HOS.SystemState;
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2019-04-16 01:22:55 +02:00
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using Ryujinx.HLE.HOS.Services;
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2019-02-11 13:00:32 +01:00
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using Ryujinx.HLE.Input;
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using Ryujinx.UI.Input;
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using System;
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using System.IO;
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using System.Threading.Tasks;
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using Utf8Json;
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using Utf8Json.Resolvers;
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namespace Ryujinx
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{
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public class Configuration
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{
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/// <summary>
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/// The default configuration instance
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/// </summary>
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public static Configuration Instance { get; private set; }
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/// <summary>
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/// Dumps shaders in this local directory
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/// </summary>
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public string GraphicsShadersDumpPath { get; private set; }
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/// <summary>
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/// Enables printing debug log messages
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/// </summary>
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public bool LoggingEnableDebug { get; private set; }
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/// <summary>
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/// Enables printing stub log messages
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/// </summary>
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public bool LoggingEnableStub { get; private set; }
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/// <summary>
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/// Enables printing info log messages
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/// </summary>
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public bool LoggingEnableInfo { get; private set; }
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/// <summary>
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/// Enables printing warning log messages
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/// </summary>
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public bool LoggingEnableWarn { get; private set; }
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/// <summary>
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/// Enables printing error log messages
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/// </summary>
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public bool LoggingEnableError { get; private set; }
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2019-06-16 03:31:18 +02:00
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/// <summary>
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/// Enables printing guest log messages
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/// </summary>
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public bool LoggingEnableGuest { get; private set; }
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/// <summary>
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/// Enables printing FS access log messages
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/// </summary>
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public bool LoggingEnableFsAccessLog { get; private set; }
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// Controls which log messages are written to the log targets
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/// </summary>
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public LogClass[] LoggingFilteredClasses { get; private set; }
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/// <summary>
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/// Enables or disables logging to a file on disk
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/// </summary>
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public bool EnableFileLog { get; private set; }
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/// <summary>
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/// Change System Language
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/// </summary>
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public SystemLanguage SystemLanguage { get; private set; }
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/// <summary>
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/// Enables or disables Docked Mode
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/// </summary>
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public bool DockedMode { get; private set; }
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2019-05-30 22:27:43 +02:00
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/// <summary>
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2019-07-02 04:39:22 +02:00
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/// Enables or disables Discord Rich Presence
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2019-05-30 22:27:43 +02:00
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/// </summary>
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2019-07-02 04:39:22 +02:00
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public bool EnableDiscordIntegration { get; private set; }
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2019-05-30 22:27:43 +02:00
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// Enables or disables Vertical Sync
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/// </summary>
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public bool EnableVsync { get; private set; }
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/// <summary>
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/// Enables or disables multi-core scheduling of threads
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/// </summary>
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2019-02-16 09:37:22 +01:00
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public bool EnableMulticoreScheduling { get; private set; }
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// Enables integrity checks on Game content files
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/// </summary>
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public bool EnableFsIntegrityChecks { get; private set; }
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2019-06-16 03:31:18 +02:00
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/// <summary>
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/// Enables FS access log output to the console. Possible modes are 0-3
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/// </summary>
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public int FsGlobalAccessLogMode { get; private set; }
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2019-02-28 03:03:31 +01:00
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/// <summary>
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Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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/// Use old ChocolArm64 ARM emulator
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2019-02-28 03:03:31 +01:00
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/// </summary>
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
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public bool EnableLegacyJit { get; private set; }
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2019-02-28 03:03:31 +01:00
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2019-04-16 01:22:55 +02:00
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/// <summary>
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/// Enable or disable ignoring missing services
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/// </summary>
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public bool IgnoreMissingServices { get; private set; }
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// The primary controller's type
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/// </summary>
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2019-07-22 19:15:46 +02:00
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public ControllerStatus ControllerType { get; private set; }
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2019-02-11 13:00:32 +01:00
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2019-05-03 01:29:01 +02:00
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/// <summary>
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/// Enable or disable keyboard support (Independent from controllers binding)
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/// </summary>
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public bool EnableKeyboard { get; private set; }
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// Keyboard control bindings
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/// </summary>
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public NpadKeyboard KeyboardControls { get; private set; }
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/// <summary>
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/// Controller control bindings
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/// </summary>
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2019-08-05 20:58:27 +02:00
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public UI.Input.NpadController JoystickControls { get; private set; }
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2019-02-11 13:00:32 +01:00
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/// <summary>
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/// Loads a configuration file from disk
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/// </summary>
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/// <param name="path">The path to the JSON configuration file</param>
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public static void Load(string path)
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{
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var resolver = CompositeResolver.Create(
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new[] { new ConfigurationEnumFormatter<Key>() },
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new[] { StandardResolver.AllowPrivateSnakeCase }
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);
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using (Stream stream = File.OpenRead(path))
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{
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Instance = JsonSerializer.Deserialize<Configuration>(stream, resolver);
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}
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}
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/// <summary>
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/// Loads a configuration file asynchronously from disk
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/// </summary>
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/// <param name="path">The path to the JSON configuration file</param>
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public static async Task LoadAsync(string path)
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{
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var resolver = CompositeResolver.Create(
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new[] { new ConfigurationEnumFormatter<Key>() },
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new[] { StandardResolver.AllowPrivateSnakeCase }
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);
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using (Stream stream = File.OpenRead(path))
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{
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Instance = await JsonSerializer.DeserializeAsync<Configuration>(stream, resolver);
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}
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}
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/// <summary>
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/// Configures a <see cref="Switch"/> instance
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/// </summary>
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/// <param name="device">The instance to configure</param>
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public static void Configure(Switch device)
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{
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if (Instance == null)
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{
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throw new InvalidOperationException("Configuration has not been loaded yet.");
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}
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GraphicsConfig.ShadersDumpPath = Instance.GraphicsShadersDumpPath;
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Logger.AddTarget(new AsyncLogTargetWrapper(
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new ConsoleLogTarget(),
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1000,
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AsyncLogTargetOverflowAction.Block
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));
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if (Instance.EnableFileLog)
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{
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Logger.AddTarget(new AsyncLogTargetWrapper(
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2019-02-13 00:24:11 +01:00
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new FileLogTarget(Path.Combine(Program.ApplicationDirectory, "Ryujinx.log")),
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2019-02-11 13:00:32 +01:00
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1000,
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AsyncLogTargetOverflowAction.Block
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));
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}
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2019-06-16 03:31:18 +02:00
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Logger.SetEnable(LogLevel.Debug, Instance.LoggingEnableDebug);
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|
|
|
Logger.SetEnable(LogLevel.Stub, Instance.LoggingEnableStub);
|
|
|
|
Logger.SetEnable(LogLevel.Info, Instance.LoggingEnableInfo);
|
|
|
|
Logger.SetEnable(LogLevel.Warning, Instance.LoggingEnableWarn);
|
|
|
|
Logger.SetEnable(LogLevel.Error, Instance.LoggingEnableError);
|
|
|
|
Logger.SetEnable(LogLevel.Guest, Instance.LoggingEnableGuest);
|
|
|
|
Logger.SetEnable(LogLevel.AccessLog, Instance.LoggingEnableFsAccessLog);
|
2019-02-11 13:00:32 +01:00
|
|
|
|
|
|
|
if (Instance.LoggingFilteredClasses.Length > 0)
|
|
|
|
{
|
|
|
|
foreach (var logClass in EnumExtensions.GetValues<LogClass>())
|
|
|
|
{
|
|
|
|
Logger.SetEnable(logClass, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
foreach (var logClass in Instance.LoggingFilteredClasses)
|
|
|
|
{
|
|
|
|
Logger.SetEnable(logClass, true);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-02 04:39:22 +02:00
|
|
|
device.System.State.DiscordIntegrationEnabled = Instance.EnableDiscordIntegration;
|
2019-05-30 22:27:43 +02:00
|
|
|
|
2019-02-11 13:00:32 +01:00
|
|
|
device.EnableDeviceVsync = Instance.EnableVsync;
|
|
|
|
|
|
|
|
device.System.State.DockedMode = Instance.DockedMode;
|
|
|
|
|
|
|
|
device.System.State.SetLanguage(Instance.SystemLanguage);
|
|
|
|
|
2019-02-16 09:37:22 +01:00
|
|
|
if (Instance.EnableMulticoreScheduling)
|
2019-02-11 13:00:32 +01:00
|
|
|
{
|
|
|
|
device.System.EnableMultiCoreScheduling();
|
|
|
|
}
|
|
|
|
|
|
|
|
device.System.FsIntegrityCheckLevel = Instance.EnableFsIntegrityChecks
|
|
|
|
? IntegrityCheckLevel.ErrorOnInvalid
|
|
|
|
: IntegrityCheckLevel.None;
|
|
|
|
|
2019-06-16 03:31:18 +02:00
|
|
|
device.System.GlobalAccessLogMode = Instance.FsGlobalAccessLogMode;
|
|
|
|
|
Add a new JIT compiler for CPU code (#693)
* Start of the ARMeilleure project
* Refactoring around the old IRAdapter, now renamed to PreAllocator
* Optimize the LowestBitSet method
* Add CLZ support and fix CLS implementation
* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks
* Implement the ByteSwap IR instruction, and some refactoring on the assembler
* Implement the DivideUI IR instruction and fix 64-bits IDIV
* Correct constant operand type on CSINC
* Move division instructions implementation to InstEmitDiv
* Fix destination type for the ConditionalSelect IR instruction
* Implement UMULH and SMULH, with new IR instructions
* Fix some issues with shift instructions
* Fix constant types for BFM instructions
* Fix up new tests using the new V128 struct
* Update tests
* Move DIV tests to a separate file
* Add support for calls, and some instructions that depends on them
* Start adding support for SIMD & FP types, along with some of the related ARM instructions
* Fix some typos and the divide instruction with FP operands
* Fix wrong method call on Clz_V
* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes
* Implement SIMD logical instructions and more misc. fixes
* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations
* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes
* Implement SIMD shift instruction and fix Dup_V
* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table
* Fix check with tolerance on tester
* Implement FP & SIMD comparison instructions, and some fixes
* Update FCVT (Scalar) encoding on the table to support the Half-float variants
* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes
* Use old memory access methods, made a start on SIMD memory insts support, some fixes
* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes
* Fix arguments count with struct return values, other fixes
* More instructions
* Misc. fixes and integrate LDj3SNuD fixes
* Update tests
* Add a faster linear scan allocator, unwinding support on windows, and other changes
* Update Ryujinx.HLE
* Update Ryujinx.Graphics
* Fix V128 return pointer passing, RCX is clobbered
* Update Ryujinx.Tests
* Update ITimeZoneService
* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks
* Use generic GetFunctionPointerForDelegate method and other tweaks
* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics
* Remove some unused code on the assembler
* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler
* Add hardware capability detection
* Fix regression on Sha1h and revert Fcm** changes
* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator
* Fix silly mistake introduced on last commit on CpuId
* Generate inline stack probes when the stack allocation is too large
* Initial support for the System-V ABI
* Support multiple destination operands
* Fix SSE2 VectorInsert8 path, and other fixes
* Change placement of XMM callee save and restore code to match other compilers
* Rename Dest to Destination and Inst to Instruction
* Fix a regression related to calls and the V128 type
* Add an extra space on comments to match code style
* Some refactoring
* Fix vector insert FP32 SSE2 path
* Port over the ARM32 instructions
* Avoid memory protection races on JIT Cache
* Another fix on VectorInsert FP32 (thanks to LDj3SNuD
* Float operands don't need to use the same register when VEX is supported
* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks
* Some nits, small improvements on the pre allocator
* CpuThreadState is gone
* Allow changing CPU emulators with a config entry
* Add runtime identifiers on the ARMeilleure project
* Allow switching between CPUs through a config entry (pt. 2)
* Change win10-x64 to win-x64 on projects
* Update the Ryujinx project to use ARMeilleure
* Ensure that the selected register is valid on the hybrid allocator
* Allow exiting on returns to 0 (should fix test regression)
* Remove register assignments for most used variables on the hybrid allocator
* Do not use fixed registers as spill temp
* Add missing namespace and remove unneeded using
* Address PR feedback
* Fix types, etc
* Enable AssumeStrictAbiCompliance by default
* Ensure that Spill and Fill don't load or store any more than necessary
2019-08-08 20:56:22 +02:00
|
|
|
device.System.UseLegacyJit = Instance.EnableLegacyJit;
|
2019-02-28 03:03:31 +01:00
|
|
|
|
2019-04-16 01:22:55 +02:00
|
|
|
ServiceConfiguration.IgnoreMissingServices = Instance.IgnoreMissingServices;
|
|
|
|
|
2019-08-05 20:58:27 +02:00
|
|
|
if (Instance.JoystickControls.Enabled)
|
2019-02-11 13:00:32 +01:00
|
|
|
{
|
2019-08-05 20:58:27 +02:00
|
|
|
if (!Joystick.GetState(Instance.JoystickControls.Index).IsConnected)
|
2019-02-11 13:00:32 +01:00
|
|
|
{
|
2019-08-05 20:58:27 +02:00
|
|
|
Instance.JoystickControls.SetEnabled(false);
|
2019-02-11 13:00:32 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-07-02 04:39:22 +02:00
|
|
|
device.Hid.InitializePrimaryController(Instance.ControllerType);
|
|
|
|
device.Hid.InitializeKeyboard();
|
2019-02-11 13:00:32 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
private class ConfigurationEnumFormatter<T> : IJsonFormatter<T>
|
|
|
|
where T : struct
|
|
|
|
{
|
|
|
|
public void Serialize(ref JsonWriter writer, T value, IJsonFormatterResolver formatterResolver)
|
|
|
|
{
|
|
|
|
formatterResolver.GetFormatterWithVerify<string>()
|
|
|
|
.Serialize(ref writer, value.ToString(), formatterResolver);
|
|
|
|
}
|
|
|
|
|
|
|
|
public T Deserialize(ref JsonReader reader, IJsonFormatterResolver formatterResolver)
|
|
|
|
{
|
|
|
|
if (reader.ReadIsNull())
|
|
|
|
{
|
|
|
|
return default(T);
|
|
|
|
}
|
|
|
|
|
2019-07-02 04:39:22 +02:00
|
|
|
string enumName = formatterResolver.GetFormatterWithVerify<string>()
|
|
|
|
.Deserialize(ref reader, formatterResolver);
|
2019-02-11 13:00:32 +01:00
|
|
|
|
2019-07-02 04:39:22 +02:00
|
|
|
if (Enum.TryParse<T>(enumName, out T result))
|
2019-02-11 13:00:32 +01:00
|
|
|
{
|
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
return default(T);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|