1
0
mirror of synced 2024-12-18 18:35:54 +01:00
Commit Graph

10 Commits

Author SHA1 Message Date
RVC-Boss
ec29cf8d65
Add files via upload 2023-10-08 18:31:09 +08:00
RVC-Boss
330ea00e5c
Update modules.py 2023-10-08 18:11:48 +08:00
Disty0
0c94f60093
Feature: Intel ARC GPU support with IPEX (#1204)
* Initial Intel ARC support with IPEX

* Fix infer

* Fix train model

* Cleanup

* Cleanup

* Update README

* Make pylint happy

* Move dataloader fix to hijacks

* Fix torch.linalg.solve

* Fix SDP

* Add has_xpu to config.py

* Revert return_xpu fix
2023-09-09 12:00:29 +08:00
github-actions[bot]
dace5a6f99
Format code (#1162)
Co-authored-by: github-actions[bot] <github-actions[bot]@users.noreply.github.com>
2023-09-02 11:50:52 +08:00
源文雨
04a33b9709 fix: 卸载音色省显存
顺便将所有print换成了统一的logger
2023-09-01 15:18:08 +08:00
源文雨
8ffdcb0128 fix: index_root searching
close #1147
2023-09-01 14:11:55 +08:00
RVC-Boss
8054281b24
Add files via upload 2023-08-30 17:46:45 +08:00
Ftps
58e32b6def format 2023-08-28 16:08:31 +09:00
Tps-F
cb42c6990b Apply Code Formatter Change 2023-08-19 10:58:39 +00:00
Ftps
0de947cf70 uvr5 modules 2023-08-19 19:57:30 +09:00